Build-Up Circuit Board Layers for Fine Pitch and Flatness
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Solution Overview
Problem
Conventional methods for manufacturing redistribution layers in semiconductor packages face challenges such as fragile fine lines leading to focus errors, reduced yield rates, and issues with conductivity and noise due to the use of tin balls, which hinder high-frequency signal integrity and increase manufacturing complexity.
Innovation Solution
A manufacturing method involving the formation of a first build-up layer with finer circuits on a carrier, followed by a second build-up layer, which is then attached to a core layer, using conductive pastes for connection, ensuring high flatness and uniformity, and eliminating the need for tin balls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple build-up layers are formed sequentially on a core layer to achieve fine line pitch redistribution layer, then the interconnection density and signal routing capability are improved, but the flatness of the build-up layers deteriorates causing focus errors during exposure
Solution Approach 1:
The patent divides the build-up process into two independent segments: first build-up layers (coarser pitch) and second build-up layers (finer pitch). Each segment is formed separately with its own carrier support, allowing independent flatness control for each segmentation, thus resolving the cumulative flatness degradation problem.
Solution Approach 2:
The patent introduces a carrier as an intermediary support structure that holds the first build-up layers during formation. This carrier provides a stable, flat base that prevents the build-up layers from sagging or deforming, maintaining flatness even as multiple layers are stacked.
2Ease of manufacture
If tin balls are used as adhesive means to attach redistribution layer, then the attachment process is simplified, but the conductivity decreases and noise increases during high-frequency transmission
Solution Approach 1:
The patent changes the material parameter of the adhesive from tin balls (solder) to conductive paste. This material substitution fundamentally alters the electrical properties, providing continuous copper-to-copper bonding that maintains high conductivity and low noise for high-frequency signals while still achieving reliable attachment.
3Quantity of substance
If the number of build-up layers is increased to achieve fine line width and spacing, then the interconnection density is improved, but the yield rate decreases due to focus errors
Solution Approach 1:
The patent segments the high-density interconnection requirement into two parts: coarse first build-up layers for structural support and routing, and fine second build-up layers for high-density signal routing. This segmentation allows each layer type to be optimized independently, maintaining high yield rate while achieving the required interconnection density.
Solution Approach 2:
The patent resolves the density-flatness contradiction by adding a dimensional element - using a carrier substrate as a separate support dimension. This allows the first build-up layers to be formed with carrier support maintaining flatness, while the second build-up layers achieve fine pitch requirements, thereby maintaining both high density and high yield rate.
Data Source
AI summary
A manufacturing method for circuit board structure includes steps of providing a carrier, forming a first build-up layer including a plurality of first circuits, forming a second build-up layer including a plurality of second circuits on a side of the first build-up layer located away from the carrier, attaching a side of the second build-up layer located away from the first build-up layer to a core layer, and removing the carrier from the first build-up layer, where the first circuits are finer than the second circuits.