Build-Up Semiconductor Substrate with Mixed L/S Interconnects
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Solution Overview
Problem
Current laminate substrates face challenges in supporting high-power processors due to limitations in thermal conductivity, coefficient of thermal expansion (CTE) mismatch, and the inability to achieve ultrafine line widths and spaces, leading to reliability issues and increased costs in high-layer, large-substrate applications for advanced ICs and AI systems.
Innovation Solution
The development of large, high-layer-count, ultrafine line width/space laminate substrates with embedded silicon interconnects and active components, utilizing low-CTE, high-thermal-conductivity materials like clad metals and ceramics, and integrating voltage regulators within the substrate to enhance thermal management and reduce CTE mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If laminate substrates use conventional BT/ABF resins and panel-level build-up processes, then manufacturing is easier and costs are lower, but thermal conductivity is poor (0.3-0.6 W/(m·K)) and cannot support high-power processors
Solution Approach 1:
The patent employs composite material structures combining multiple resin systems (BT resin, ABF resin, polyimide) with different thermal and mechanical properties. The core layer uses BT resin for structural stability, while build-up layers use ABF and polyimide for fine-line capabilities and flexibility, achieving optimized thermal conductivity and mechanical performance
Solution Approach 2:
The substrate structure implements local quality differentiation with a core layer optimized for thermal management and mechanical strength, while build-up layers are optimized for fine-line circuit fabrication. This allows different regions of the substrate to serve specialized functions - the core provides thermal pathways while build-up layers provide electrical interconnects
2Adaptability or versatility
If laminate substrates have large sizes and high layer counts to support advanced ICs, then device capability is improved, but substrate yields decrease and costs increase due to panel-level processing limitations
Solution Approach 1:
The substrate is segmented into a core layer and multiple build-up layers, allowing independent optimization and processing of each layer. This segmentation enables the core to be manufactured at panel level while build-up layers can be selectively added in smaller batches, improving overall yield and reducing waste
3Ease of operation
If laminate substrates have high CTE (16-18 ppm/°C.) to match laminate material properties, then material compatibility is improved, but solder joint reliability deteriorates due to CTE mismatch with silicon chips
Solution Approach 1:
The patent modifies the CTE parameter of the substrate by selecting and combining materials with specific thermal expansion properties. The core layer and build-up layers are chosen to achieve an effective CTE that is lower than conventional laminates, reducing the mismatch with silicon chips while maintaining laminate processing compatibility
Solution Approach 2:
By using composite material construction with BT resin, ABF resin, and polyimide in specific combinations and thicknesses, the substrate achieves a tailored effective CTE that balances compatibility with both laminate processing and silicon chip attachment, reducing thermal stress on solder joints
4Manufacturing precision
If laminate substrates achieve ultrafine L/S (2 μm/2 μm and beyond) to support advanced IC pitches, then IC scaling is enabled, but manufacturing precision requirements increase and yields decrease
Solution Approach 1:
The substrate fabrication is segmented into core layer manufacturing at panel level followed by selective build-up layer formation. This allows the majority of the substrate to be produced with relaxed tolerances, while only specific regions require ultrafine L/S capabilities, thereby maintaining high yields while enabling advanced pitch support
Solution Approach 2:
Ultrafine L/S capabilities are implemented locally in the build-up layers where fine-pitch interconnects are required, while the core layer maintains conventional dimensions. This localized approach to precision manufacturing reduces the overall difficulty and cost of achieving ultrafine pitches without compromising substrate yield
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient heat dissipation, reduces stress on solder joints, and improves reliability and energy efficiency by matching thermal expansion with silicon, while allowing for finer pitches and higher thermal conductivity, addressing the limitations of existing substrates in supporting advanced ICs and AI applications.
Implementation Method 1
high effective thermal conductivities
Implementation Method 2
coefficient of thermal expansion (CTE) that more closely matches the CTE of silicon
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a core, a first build-up structure and an input/output conductive structure. The core has a first surface and a second surface. The first build-up structure is formed on the first surface and/or the second surface and includes a plurality of first build-up conductive portions. The input/output conductive structure is formed above the first build-up structure and includes a plurality of input/output conductive portions. An input/output line width/line spacing (L/S) of the input/output conductive portions is different from a first L/S of the first build-up conductive portions.