Buildup Process Vias for Electronic Chip Package Density
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Solution Overview
Problem
Conventional electrical interconnect drilling methods, such as laser and mechanical drilling, result in significant variations in via size and position, limiting the potential increase in electronic package density due to alignment and size tolerances, especially as component sizes decrease.
Innovation Solution
The formation of vias through a semi-additive process (SAP) where the via is created prior to or concurrently with the insulator layer, allowing for precise control of size and shape, similar to the fabrication process of traces, and enabling vias to be configured and sized similarly to input/output pads and conductive traces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional drilling methods (laser or mechanical) are used to create vias, then the process is simple and fast, but the positional, size, and shape accuracy varies significantly
Solution Approach 1:
Instead of drilling holes through the insulator layer and then filling them with conductor (conventional approach), the patent inverts the process by first forming the conductor layer and then depositing the insulator layer over it. This inversion allows the via structure to be defined by the conductor pattern itself rather than by drilling, achieving much higher precision in positional, size, and shape control while maintaining process simplicity through standard deposition techniques.
2Productivity
If via size is reduced to increase trace density, then the density increases, but the drilling alignment tolerance becomes insufficient
Solution Approach 1:
The patent replaces the mechanical drilling process with a deposition-based fabrication process. Instead of using mechanical or laser drilling to create vias, the invention uses sequential deposition of conductor and insulator layers to form via structures. This substitution eliminates the alignment tolerance limitations of drilling processes and enables much smaller via sizes, thereby increasing trace density on the board.
3Shape
If drilling processes are used to create vias, then the process is conventional and well-established, but the size and shape control of vias is poor
Solution Approach 1:
The patent applies preliminary action by first forming the conductor layer with the desired via pattern before depositing the insulator layer. This preliminary conductor formation establishes precise size and shape control for the vias, as the conductor pattern defines the via geometry. The insulator is then deposited conformally over this predefined pattern, maintaining the precision achieved in the preliminary conductor formation step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces positional and size variations, enabling higher density and consistent via formation with regular, configurable shapes and sizes, improving the utility and efficiency of electronic package design.
Implementation Method 1
depositing a metal layer within the cavity
Implementation Method 2
The metal layer can be formed from copper using an electroless or electrolytic deposition process
Data Source
AI summary
This disclosure relates generally to an electronic chip package that can include a die and a buildup layer substantially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the buildup layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic chip package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic chip package different from the first major surface.