Built-in Memory Current Test Circuit Reducing SOC Stress Test Time
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Solution Overview
Problem
Conventional memory testing methods require extra time and resources due to the need for resetting test currents during stress testing, especially when testing multiple memories in a system on a chip (SOC), as each memory requires different test currents, leading to prolonged total test time.
Innovation Solution
A built-in self-test circuit with a dynamic current source that generates test currents based on a current control code, allowing for integrated functional and stress testing without the need for extra pins or resetting, enabling parallel testing of multiple memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory testing methods are used with external reference current source, then functional testing can be performed, but stress testing requires extra time for current resetting and selection
Solution Approach 1:
The patent extracts the current selection and control functionality from the external ATE equipment and relocates it to an integrated current control circuit built within the memory chip itself. This allows the chip to autonomously select and switch between different test currents without requiring external intervention or resetting, thereby eliminating the time loss associated with external current source reconfiguration during stress testing.
Solution Approach 2:
The memory chip incorporates a self-contained current control circuit that automatically manages test current selection and switching based on internal control signals. The chip performs self-testing with multiple currents without requiring external ATE equipment to reset or reconfigure current sources, enabling autonomous stress testing that reduces overall test time while maintaining reliability.
2Reliability
If multiple memories in SOC are tested sequentially with different test currents, then each memory can be stress tested, but total test time becomes very long
Solution Approach 1:
The patent segments the current control functionality into separate, independent current control circuits for each memory unit within the SOC. Each memory can independently select and apply its required test current through its dedicated control circuit, enabling parallel stress testing of multiple memories simultaneously. This segmentation eliminates the sequential testing bottleneck and dramatically improves overall testing throughput while maintaining comprehensive stress test coverage.
3Adaptability or versatility
If extra pins are added to reference current source for current selection, then appropriate test currents can be provided, but device complexity increases
Solution Approach 1:
The patent merges the current selection and control functions into the internal architecture of the memory chip, combining what were previously separate external ATE functions with the chip's internal circuitry. The current control circuit integrates current generation, selection, and switching capabilities within the chip, eliminating the need for extra external pins while maintaining full adaptability for different test current requirements.
Solution Approach 2:
The internal current control circuit is designed with multi-functionality, serving multiple purposes: it provides different test currents for functional testing, stress testing, and can dynamically switch between currents based on test requirements. This universal circuit replaces what would have required multiple dedicated external pins and current source configurations, reducing device complexity while maintaining versatility.
Data Source
AI summary
A built-in memory current test circuit to test a memory on a chip is disclosed, comprising a built-in self-test circuit and a dynamic current generation module. The built-in self-test circuit is disposed on the chip to receive and process a test signal and generate a control signal to control operation of the memory and a current control code. The dynamic current generation module, also disposed on the chip, produces a test current into the memory based on the current control code. The current switch time is reduced in the built-in memory current test circuit, and an integrated test combining functional and stress tests can thus be performed.