Built-in Self-Test for DRAM Timing Parameter Measurement
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Solution Overview
Problem
Existing integrated circuit testing environments face difficulties in accurately measuring timing parameters, particularly at high operating speeds, due to signal propagation delays in long cables and the inability to simulate actual operating conditions, which can lead to timing parameters deviating from specifications over time.
Innovation Solution
A built-in self-test system within the integrated circuit using a multi-phase signal generator and phase detectors to determine the relative timing between digital signals, allowing for accurate measurement of timing parameters like tDQSQ and tQH, even at high speeds and in real-use conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external testers with long cables are used for testing, then testing can be performed with standard equipment, but signal propagation delays increase and timing measurement precision deteriorates
Solution Approach 1:
The patent extracts the timing measurement function from the external tester system and implements it directly within the integrated circuit device through built-in test circuits. This removes the need for long external cables and their associated propagation delays, enabling precise timing measurements to be performed internally without the time loss introduced by external testing equipment.
Solution Approach 2:
The patent introduces delay elements as intermediaries between the test signal sources and the measurement points. These delay elements provide controlled time delays that allow for accurate measurement of timing parameters by creating known reference delays, thereby enabling precise timing characterization without being affected by external cable delays.
2Adaptability or versatility
If testing is performed in standard testing environments, then testing can be conducted during manufacturing, but the ability to simulate actual operating conditions deteriorates
Solution Approach 1:
The patent implements a universal test circuit architecture that can operate in multiple modes - both in the standard manufacturing testing environment and in actual operating conditions. The built-in test circuits can be activated during manufacturing for initial characterization and then remain functional throughout the device's operational life, enabling continuous verification under real operating conditions and ensuring long-term reliability.
Solution Approach 2:
The patent performs preliminary timing characterization during manufacturing using the built-in test circuits, establishing baseline timing parameters before the device is deployed. This preliminary action allows for early detection of timing issues and provides reference data for comparing against future measurements taken during actual operation, enabling proactive reliability management.
3Speed
If high operating speeds are used, then device performance improves, but timing measurement difficulty increases due to reduced timing margins
Solution Approach 1:
The patent measures timing parameters in the time domain by converting timing relationships into measurable time intervals using delay elements and phase detectors. By operating in this extended time dimension rather than directly measuring at the original high-speed signal edges, the system can accurately characterize timing parameters even at very high operating speeds where traditional measurement methods would fail due to insufficient timing margins.
Data Source
AI summary
A built-in self-test system for a dynamic random access memory device using a data output register of the memory device to apply test signals to data bus terminals and a data strobe terminal of the memory device responsive to respective clock signals. The clock signal are generated by a test system oscillator and coupled through a clock tree of the memory device. The test system further includes a selector that sequentially selects each of the test signals applied to the data bus terminals and applies the selected test signal to a multi-phase generator. The multi-phase generator delays the selected signal by different time to generate a set of delayed signals. The phases of the delayed signals are compared to the test signal applied to the data strobe terminal to determine the delay of the compared signals relative to each other, thereby determining the timing parameter.