Built-in Self-Test Interconnect Interface for IC Packaging

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Solution Overview

Problem

The complexity of interconnect interfaces in IC packaging poses a challenge for efficient and easy testing of packet transmission paths, as existing methods struggle to effectively detect issues like noise, interrupts, and signal attenuation.

Innovation Solution

A built-in self-test (BIST) method and system that utilize gold patterns and headers to generate test patterns, transmit them through tested paths, and compare received patterns to determine test results, including bit error rates, facilitating efficient testing of packet transmission paths in ICs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional testing methods are used for interconnect interfaces, then testing can be performed with existing equipment, but the testing process becomes complex and inefficient for delicate interconnect interfaces

Engineering Contradiction:
Improvetesting efficiencyVSAvoidtesting complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements built-in self-test (BIST) functionality where the interconnect interface tests itself using integrated test pattern generation and comparison circuits. The transmitting end generates test patterns with headers, transmits them through the interconnect interface, and the receiving end compares received patterns against expected gold patterns to detect errors, enabling autonomous testing without external equipment.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The test pattern generation module and pattern comparison module are designed to work with various interconnect interface configurations and packet formats. The BIST mechanism can test different transmission paths (first tested path and second tested path) and handle multiple gold patterns, making the testing system universally applicable to different interface designs while maintaining simplicity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Quantity of substance

If the interconnect interface design is made more delicate to meet IC packaging density requirements, then packaging density improves, but testing the packet transmission path becomes more difficult

Engineering Contradiction:
Improvepackaging densityVSAvoidtesting difficulty
Core Design Contradiction:
Quantity of substanceVSDifficulty of detecting and measuring

Solution Approach 1:

The patent segments the test pattern into distinct components: a header portion and a data portion (gold pattern). The header contains identification information that allows the receiving end to select the appropriate gold pattern for comparison. This segmentation enables systematic testing of delicate interconnect interfaces by breaking down the complex transmission verification into manageable pattern generation, transmission, and comparison stages.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The header acts as an intermediary between the test pattern transmission and the gold pattern selection process. The header contains identification information that mediates the matching process between transmitted patterns and stored gold patterns, enabling the receiving end to automatically select the correct reference pattern for comparison without complex external testing equipment.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If comprehensive testing of packet transmission paths is implemented, then detection accuracy improves, but the testing mechanism becomes more complex

Engineering Contradiction:
Improvedetection accuracyVSAvoidtesting mechanism complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent stores multiple gold patterns (first gold pattern, second gold pattern, third gold pattern) in advance at the receiving end, each corresponding to different test scenarios and identified by specific headers. This preliminary preparation of reference patterns enables comprehensive testing of various transmission conditions without requiring complex real-time pattern generation or external testing equipment, achieving high detection accuracy through pre-configured reference data.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12013771B2Method and interconnect interface for built-in self-test
Publication Date: 2024.06.18 VIA ALLIANCE SEMICON CO LTD
  • US12013771B2 patent drawing
  • US12013771B2 patent drawing
  • US12013771B2 patent drawing

AI summary

A method for built-in self-test, including the following operations: at a transmitting part, selecting a gold pattern, generating a test pattern using the gold pattern and a header corresponding to the gold pattern, and transmitting the test pattern to a receiving part via a tested path; and at a receiving part, parsing the header and a received pattern from the test pattern received, obtaining the gold pattern corresponding to the header based on the header parsed, and obtaining a test result of the tested path by comparing the gold pattern to the received pattern.