Built-in Self-Test Logic for Memory Modules
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Solution Overview
Problem
Existing semiconductor memory technologies lack effective built-in self-test logic for efficiently detecting defects in memory modules, particularly during manufacturing.
Innovation Solution
A memory device with improved built-in self-test logic, including a test logic circuit that generates patterns with diagonal intervals to intensify interference between adjacent memory cells, facilitating quick defect detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional test patterns are used, then the test coverage is limited, but the defect detection efficiency is insufficient
Solution Approach 1:
The patent introduces diagonal patterns with intervals (I=2d) that extend the test beyond conventional row-by-row or column-by-column scanning. This dimensional approach creates interference patterns that propagate diagonally across the memory array, enabling detection of defects that conventional linear scanning patterns miss, thereby improving both defect detection efficiency and test coverage
Solution Approach 2:
The patent changes the test pattern parameters by introducing diagonal intervals with specific spacing (I=2d) between pattern elements. This parameter modification creates controlled interference between adjacent memory cells, allowing the test to detect defects through interference-based detection mechanisms rather than direct signal reading, thus enhancing defect detection efficiency
2Reliability
If built-in self-test logic is added, then defect detection capability is improved, but device complexity increases
Solution Approach 1:
The patent implements built-in self-test logic that enables the memory device to test itself without requiring external test equipment. The test logic circuit generates diagonal patterns, applies them to the memory array, and automatically detects defects through interference measurement, allowing the device to perform its own reliability verification and reducing the need for complex external testing infrastructure
Solution Approach 2:
The test logic circuit is designed to perform multiple functions: generating diagonal test patterns, applying them to the memory array through input/output circuits, measuring interference effects, and detecting defects. This multi-functional approach consolidates what would otherwise require separate dedicated test components into a single integrated circuit, improving reliability while limiting the increase in overall device complexity
Data Source
AI summary
A memory device may include a memory module including a memory cell array and a plurality of input/output circuits and a test logic circuit configured to perform a self-test on the memory module, wherein the test logic circuit may include a pattern generator configured to generate a pattern of the memory cell array including diagonal patterns with interval corresponding to a second value I based on a first value d, and I=2d.