Built-in Self-Test Circuit Reduces Semiconductor Test Time
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Solution Overview
Problem
The increasing complexity of semiconductor device design and manufacturing processes has led to longer and more costly testing times, necessitating more efficient methods for evaluating semiconductor device reliability before and after packaging.
Innovation Solution
A semiconductor system comprising a first and second semiconductor device, where the second device includes a command processor, bank active signal generation circuit, address generator, and memory area, which repeatedly writes and reads data from memory cells in response to a test mode signal, allowing for stress application and defect detection/recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If design schemes and manufacturing processes become more complicated to achieve higher integration, then device functionality and integration are improved, but test time and complexity increase
Solution Approach 1:
The patent implements built-in self-test (BIST) circuits within the semiconductor device that enable the device to test itself automatically. The BIST circuit includes test pattern generators, response analyzers, and control logic that can autonomously generate test patterns, apply them to the device under test, and analyze the responses without external test equipment, thereby reducing test time and complexity while maintaining high integration capabilities
Solution Approach 2:
The patent incorporates test circuits and BIST functionality during the design and manufacturing stages rather than adding them later. The BIST circuit is built into the device structure along with the main functional circuits, allowing test capabilities to be prepared in advance and executed efficiently during production testing, reducing the need for time-consuming external testing procedures
2Productivity
If built-in self-test circuits are incorporated to test devices before packaging, then test efficiency is improved, but device complexity increases
Solution Approach 1:
The patent merges the BIST circuit functionality with the existing device architecture by integrating test pattern generators, response analyzers, and control logic into the same chip structure as the main functional circuits. This consolidation allows the BIST functionality to share resources with the main device operations, reducing the overall complexity increase while maintaining high test efficiency
Solution Approach 2:
The BIST circuit is designed to perform multiple testing functions and can be configured to test different portions of the device under various operating conditions. The same BIST infrastructure can execute different test patterns and analyze different response types, making the added complexity serve multiple purposes and justify the increased device complexity through enhanced testing capabilities
Data Source
AI summary
A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output a clock signal, a test mode signal and command address signals. The second semiconductor device may repeatedly write and read out data into and from a plurality of memory cells sequentially selected by addresses that are sequentially counted or may repeatedly write and read out the data into and from specific memory cells selected by a specific address among the addresses, according to the clock signal and the command address signals in response to the test mode signal.