Built-in Test Circuit for Semiconductor Wafer Testing
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Solution Overview
Problem
Semiconductor apparatuses at the wafer level are limited by the number of usable pads or pins, restricting the number of signals that can be input from external test equipment during wafer level testing, which hampers efficient testing and increases testing time.
Innovation Solution
A built-in self test circuit that can perform both burn-in stress and normal operation tests using a limited number of control signals from an external device, including a clock buffer to generate an internal clock signal and a reference voltage generation unit, allowing for internal signal generation during normal operation tests without additional design changes to the normal operation circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If external test equipment is used for wafer level testing, then comprehensive testing can be performed, but the number of input signals is limited by the number of pads or pins
Solution Approach 1:
The semiconductor apparatus performs self-testing by generating internal test signals and control signals within the device itself, eliminating the need for extensive external test equipment connections. The built-in test circuit generates address signals, clock signals, and control signals internally, allowing comprehensive testing with minimal external pad usage.
Solution Approach 2:
The limited pads or pins are designed to serve multiple functions: they handle both normal operation signals and test signals. The clock buffer and reference voltage generation unit enable the same physical interface to support both operational modes and testing modes, maximizing the utility of limited I/O resources.
2Productivity
If built-in self test circuits are added to perform comprehensive tests, then testing efficiency increases, but device complexity increases
Solution Approach 1:
The test circuit components are integrated into the existing semiconductor apparatus structure. The clock buffer, reference voltage generation unit, and address buffer group are merged with the normal operation circuitry, sharing physical resources and reducing overall device complexity while maintaining comprehensive testing capability.
Solution Approach 2:
Circuit components serve dual purposes: the clock buffer generates clock signals for both normal operation and testing, the address buffer group handles both operational addresses and test addresses, and the reference voltage generation unit supports both modes. This multi-functionality increases testing efficiency without proportionally increasing device complexity.
3Measurement precision
If additional test signals are input from external equipment, then more comprehensive testing can be performed, but the limited number of pads or pins restricts signal input
Solution Approach 1:
The apparatus generates its own test signals internally through the built-in test circuit, including address signals from the address buffer group, clock signals from the clock buffer, and control signals from the test control block. This self-service approach eliminates the need for additional external signal inputs, enabling comprehensive testing with limited pads.
Solution Approach 2:
Instead of increasing the number of physical pads (one dimension), the solution moves to internal signal generation (another dimension). The test circuit generates signals within the device, transforming the problem from external signal input to internal signal generation, thereby bypassing the pad quantity limitation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient wafer level testing with increased precision and reliability, reducing manufacturing costs by allowing normal operation tests to be performed with limited external input signals, thereby improving product quality and sorting out defective semiconductors before packaging.
Implementation Method 1
a clock buffer suitable for generating an internal clock signal, based on first and second clock signals, in a first operation mode, and generating the internal clock signal, based on the first clock signal and a reference voltage, when a normal operation test is performed in a second operation mode
Implementation Method 2
a reference voltage generation unit suitable for generating the reference voltage when the normal operation test is performed in the second operation mode
Data Source
AI summary
A semiconductor apparatus includes a clock buffer and a reference voltage generation unit. The clock buffer generates an internal clock signal, based on first and second clock signals, in a first operation mode, and generates the internal clock signal, based on the first clock signal and a reference voltage, when a normal operation test is performed in a second operation mode. The reference voltage generation unit generates the reference voltage when the normal operation test is performed in the second operation mode.