Bulb Type Recess Gate Fabrication Void Reduction
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Solution Overview
Problem
The formation of bulb type recess gates in semiconductor devices leads to voids when polysilicon electrodes are deposited, affecting electrical characteristics, and existing methods struggle to maintain the size of the bulb pattern and overlay margin with respect to the gate pattern, causing misalignment and performance issues.
Innovation Solution
A method involving a three-step etching process to form a semiconductor device with a bulb type recess, including a first recess with a vertical profile, a second recess with a wider vertical profile, and a third recess with a spherical profile, which reduces the size of the void while maintaining the bulb pattern and overlay margin, using high-density plasma etching with specific gas ratios and conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a bulb type recess gate is formed with a larger bulb pattern to increase channel area, then the channel area is widened and electrical characteristics are improved, but the size of the void formed during polysilicon deposition increases, which badly affects the electrical characteristics of the device
Solution Approach 1:
The recess profile is segmented into three distinct etching stages: first recess formation with vertical sidewalls, second recess formation with wider opening, and third recess formation with spherical bulb pattern. This segmentation allows precise control of each region's dimensions to optimize both channel area and void minimization
Solution Approach 2:
Different regions of the recess are given different local qualities through selective etching: the upper portion maintains a narrow neck for good overlay margin, the middle portion has vertical sidewalls for structural integrity, and the lower portion has a spherical bulb shape for maximum channel area. This local differentiation resolves the contradiction between large bulb size and void reduction
2Reliability
If a large neck pattern is formed to reduce the size of the void, then the void size is reduced, but the overlay margin with respect to the gate pattern is reduced, causing misalignment and exposing the upper portion of the bulb type recess
Solution Approach 1:
The etching process is segmented into three distinct stages that form different recess profiles at different depths. The first recess stage creates the upper neck region with controlled width for overlay margin, while subsequent stages create the lower bulb region. This segmentation allows the neck width to be independently optimized for overlay precision without being constrained by the bulb size requirements
Solution Approach 2:
The solution moves from a two-dimensional trade-off (neck width vs. bulb size in a single cross-section) to a three-dimensional solution where the recess profile varies with depth. The neck width at the upper portion is optimized for overlay margin, while the bulb expands at the lower portion to provide channel area, effectively resolving the contradiction by utilizing the vertical dimension
3Area of moving object
If a bulb type recess is formed by isotropically etching the semiconductor substrate under the neck pattern to create a spherical bulb pattern, then the channel area is increased, but voids are formed during polysilicon electrode deposition due to the narrower neck pattern
Solution Approach 1:
The etching process is divided into three sequential stages: first recess formation establishing the neck region, second recess formation creating vertical sidewalls, and third recess formation generating the spherical bulb pattern. This segmentation allows the bulb to be formed with controlled geometry that minimizes void space while maintaining large channel area
Solution Approach 2:
The etching parameters (gas composition, power, pressure) are changed between stages to achieve different profile characteristics. The third stage uses parameters optimized for spherical bulb formation with controlled aspect ratio, ensuring the bulb expands sufficiently for channel area while maintaining a profile that allows complete polysilicon filling without void formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the size of the void and maintains the bulb pattern and overlay margin, thereby improving the electrical characteristics of the semiconductor device by ensuring proper filling and alignment of the gate pattern.
Implementation Method 1
high-density plasma etching with specific gas ratios and conditions
Data Source
AI summary
A method for fabricating a semiconductor device includes etching a substrate to form a first recess having a micro trench, etching the substrate disposed under the first recess to form a second recess having a profile substantially vertical and a width greater than a portion of the first recess where no micro trench is formed, etching the substrate disposed under the second recess to form a third recess having a profile substantially spherical, and forming a gate pattern over a resultant recess including the first to third recesses.