Bulb-Shaped Recess Gate Fabrication for Leakage Reduction

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Solution Overview

Problem

The increasing integration scale of semiconductor devices leads to decreased channel length and increased implantation doping concentration, causing junction leakage and compromising the refresh property of the device, especially with the formation of horns at active region edges that can localize electric charges and generate leakage currents.

Innovation Solution

A method is introduced to fabricate semiconductor devices with bulb-shaped recesses by forming a mask pattern over a substrate, etching first recesses, depositing a polymer-based layer, and then using this layer as an etch mask to create wider and more rounded second recesses, eliminating horns and stress points, and forming a gate pattern over these recesses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a planar gate is formed over a flat active region, then the manufacturing process is simple, but the channel length is decreased and junction leakage increases

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidjunction leakage
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies curvature by forming a bulb-shaped recess with rounded corners instead of sharp edges. The recess is formed by etching the substrate to create a curved profile that eliminates the horn formation at the active region edges. This curved geometry prevents charge localization and reduces junction leakage while maintaining manufacturing feasibility through controlled etching processes.

Inventive Principle:
Principle #14Spheroidality (Curvature)

2Productivity

If the integration scale is increased, then the device density improves, but the channel length decreases and implantation doping concentration increases

Engineering Contradiction:
Improvedevice densityVSAvoidchannel length
Core Design Contradiction:
ProductivityVSLength of moving object

Solution Approach 1:

The patent transitions from a two-dimensional planar gate structure to a three-dimensional bulb-shaped recess structure. By etching the substrate to form a recess with depth and curved profiles, the channel length is extended in the vertical dimension while maintaining the horizontal footprint required for high device density. This dimensional transition allows simultaneous achievement of high integration scale and adequate channel length.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Length of moving object

If a typical U-shaped recess is formed, then the channel length is increased, but horns are formed at the edges causing leakage current

Engineering Contradiction:
Improvechannel lengthVSAvoidleakage current
Core Design Contradiction:
Length of moving objectVSObject-generated harmful factors

Solution Approach 1:

The patent converts the harmful horn formation into a beneficial rounded profile. Instead of allowing the etching process to create sharp edges that generate horns and leakage, the process is controlled to form a bulb-shaped recess with intentionally rounded corners. This transforms the potential harm of edge effects into a benefit by eliminating charge localization and reducing junction leakage while maintaining the extended channel length.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach increases channel length, prevents leakage currents, enhances threshold voltage, and improves refresh properties by removing horns and stress points, resulting in better electrical performance and reliability.

Implementation Method 1

forming a polymer-based layer over the sidewalls of the first recess and a top surface of the mask pattern

Methodology Applied
Scientific EffectChemical Vapor Deposition: Chemical Vapour Deposition

Data Source

PatentUS7678535B2Method for fabricating semiconductor device with recess gate
Publication Date: 2010.03.16 SK HYNIX INC
  • US7678535B2 patent drawing
  • US7678535B2 patent drawing
  • US7678535B2 patent drawing

AI summary

A method for fabricating a semiconductor device includes forming a mask pattern over a substrate; etching a certain portion of the substrate using the mask pattern as an etch mask to form a first recess having sidewalls; forming a polymer-based layer over the sidewalls of the first recess and a top surface of the mask pattern; etching the substrate beneath the first recess using the mask pattern and the polymer-based layer as an etch mask to form a second recess wider and more rounded than the first recess, the second recess and the first recess constituting a bulb-shaped recess; and forming a gate pattern over the bulb-shaped recess.