Bulb-Shaped Recess Profile for Semiconductor Leakage Reduction

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Solution Overview

Problem

In semiconductor device fabrication, the reduction in channel length and increase in implantation doping concentration lead to junction leakage and compromised refresh properties, particularly as device sizes decrease and distances between channels shorten, with the formation of horns at active region edges causing localized electric charges and leakage currents.

Innovation Solution

A method involving etching a substrate to form first recesses with a roundly projected bottom middle portion and tapered bottom edge portions, followed by forming second recesses that are wider and rounded, and then rounding the top corners, to create a bulb-shaped recess profile that increases channel length and reduces stress points, using specific gas mixtures and plasma etching conditions to achieve a micro-trench profile and improve gate insulation and pattern formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a planar gate is formed over a flat active region, then the fabrication process is simple, but the channel length is short and junction leakage increases

Engineering Contradiction:
Improvefabrication process simplicityVSAvoidchannel length
Core Design Contradiction:
Ease of manufactureVSLength of moving object

Solution Approach 1:

The etching process is segmented into multiple stages: first etching to form initial recesses, then second etching to form deeper recesses, and finally corner rounding etching. This segmented approach enables precise control of the recess profile to achieve the desired bulb-shaped structure with rounded corners, resolving the contradiction between fabrication simplicity and channel length control

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The method performs preliminary corner rounding etching after forming the recesses but before gate formation. This preliminary action prevents horn formation at the corners and ensures the active region edges are properly shaped before subsequent processing, thereby increasing channel length while maintaining fabrication feasibility

Inventive Principle:
Principle #10Preliminary action

2Area of stationary object

If the active region size is decreased to increase integration density, then device size is reduced, but horn formation at edges causes leakage current

Engineering Contradiction:
Improveactive region areaVSAvoidleakage current from horn formation
Core Design Contradiction:
Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

The method performs preliminary corner rounding etching after forming the recesses but before gate formation. This preliminary action prevents horn formation at the corners and ensures the active region edges are properly shaped before subsequent processing, thereby increasing channel length while maintaining fabrication feasibility

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The etching process applies different conditions to different regions: the corner rounding etching specifically targets the corner regions to round them, while the main recess etching affects the broader active region. This localized quality control prevents horn formation at corners while maintaining the overall recess structure, resolving the contradiction between small device size and leakage prevention

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method enhances channel length and area, increases threshold voltage, and improves refresh properties by reducing leakage currents and stress points, resulting in better electrical performance and reliability of semiconductor devices.

Implementation Method 1

etching a predetermined portion of a substrate to form a first recess having a bottom middle portion roundly projected and bottom edge portions tapered to have a micro-trench profile

Methodology Applied
Scientific EffectPlasma etching: Plasma

Data Source

PatentUS7582532B2Method for fabricating semiconductor device
Publication Date: 2009.09.01 MIMIRIP LLC
  • US7582532B2 patent drawing
  • US7582532B2 patent drawing
  • US7582532B2 patent drawing

AI summary

A method for fabricating a semiconductor device includes etching a predetermined portion of a substrate to form a first recess having a bottom middle portion roundly projected and bottom edge portions tapered to have a micro-trench profile; and etching the substrate beneath the first recess to form a second recess, the second recess being rounded and being wider than the first recess.