BULEX Contacts in FDSOI Fabrication
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Solution Overview
Problem
The step height difference between BULEX regions and SOI regions in FDSOI techniques leads to uncontrollable variations in critical dimensions, lithographical offsets, and issues like divots and crevices, causing shorts and leaks in semiconductor circuits during the fabrication of advanced semiconductor devices.
Innovation Solution
A method of forming semiconductor devices that involves providing an SOI substrate with a gate structure, partially exposing the base substrate to form bulk exposed regions after gate formation, and creating a contact structure for contacting these regions without the need for epi re-growth, thereby eliminating the step height issues and allowing for back bias contacts and diode structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If epi re-growth is performed to reduce step height between BULEX regions and SOI regions, then manufacturing precision improves, but device complexity and process time increase
Solution Approach 1:
The patent extracts and eliminates the problematic epi re-growth step from the fabrication process. By using a planarization layer deposited conformally over the step structure and then selectively removed in SOI regions, the method achieves step height reduction without requiring complex epi re-growth processes, thereby simplifying the overall device fabrication while maintaining manufacturing precision
Solution Approach 2:
The patent introduces a planarization layer as an intermediary material to manage the step height between BULEX and SOI regions. This layer is deposited conformally to fill the step and is subsequently selectively removed in SOI regions, acting as a mediator that enables precise topography control without the complexity of epi re-growth processes
2Reliability
If larger separation distance is maintained between BULEX contacts and SOI contacts to avoid shorts, then reliability improves, but area consumption increases
Solution Approach 1:
The patent applies local quality by differentiating the treatment of BULEX and SOI regions. The planarization layer is selectively removed only in SOI regions while being retained in BULEX regions, enabling precise local control of contact separation. This allows minimal separation distance to be maintained between contacts while ensuring reliability through localized topography management rather than uniform separation
Solution Approach 2:
The patent transitions from managing contact separation in the lateral plane to managing it in the vertical dimension through the planarization layer. By controlling the topography height difference between BULEX and SOI regions, the method enables closer lateral contact spacing while maintaining reliability through vertical separation, effectively utilizing the third dimension to reduce area consumption
3Ease of manufacture
If conventional fabrication processes are used with significant step heights, then ease of manufacture is maintained, but manufacturing precision deteriorates due to uncontrollable critical dimension variations
Solution Approach 1:
The patent performs preliminary planarization by depositing the planarization layer conformally over the step structure before subsequent lithography and patterning steps. This preliminary topography management eliminates the need for complex epi re-growth processes while ensuring precise critical dimension control, thereby maintaining ease of manufacture through simple deposition and removal steps rather than complex process sequences
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the distance between back bias contacts and semiconductor device contacts, enabling simultaneous implementation of back bias bulk contacts and diode structures without topography issues, thus improving fabrication precision and reducing the risk of shorts and leaks.
Implementation Method 1
an SOI substrate with an active semiconductor layer disposed on a buried oxide (BOX) layer, which is in turn formed on a base substrate material
Data Source
AI summary
The present disclosure provides, in accordance with some illustrative embodiments, a method of forming a semiconductor device, the method including providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming a gate structure on the active semiconductor layer in an active region of the SOI substrate, partially exposing the base substrate for forming at least one bulk exposed region after the gate structure is formed, and forming a contact structure for contacting the at least one bulk exposed region.