Bulk CMOS RF Switch Well Biasing for Improved Linearity
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Solution Overview
Problem
High power RF switches manufactured in bulk CMOS processes face challenges due to undesired junction capacitances that degrade linearity, despite the cost and scalability advantages of this process.
Innovation Solution
The implementation of a controllable FET in a bulk CMOS process with a well bias voltage system, allowing for switchable gate, body, and well bias voltages to manage junction capacitances, thereby reducing their negative impact on linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a bulk CMOS process is used to manufacture high power RF switches, then cost and scalability are improved, but linearity is degraded due to undesired junction capacitances
Solution Approach 1:
The patent applies dynamic biasing by switching between different well voltage levels (first well voltage level when OFF, second well voltage level when ON) and body voltage levels based on the switch state. This dynamic adjustment of voltage levels allows the bulk CMOS process to achieve linearity performance comparable to SOI processes while maintaining the cost and scalability advantages of bulk CMOS manufacturing.
Solution Approach 2:
The patent changes the electrical parameters (voltage levels) applied to the well and body terminals of the FET switch. By applying a first well voltage level and first body voltage level in the OFF state, and switching to a second well voltage level and second body voltage level in the ON state, the patent optimizes the junction capacitance characteristics to improve linearity while maintaining bulk CMOS process advantages.
2Manufacturing precision
If floating body devices are used in SOI processes, then linearity is improved due to reduced drain-body and source-body capacitances, but manufacturing cost and scalability are worsened
Solution Approach 1:
The patent copies the linearity improvement effect of floating body devices by using controlled well and body voltage levels in bulk CMOS FETs. Instead of physically creating floating body structures (as in SOI), the patent replicates the electrical behavior by dynamically biasing the well and body terminals, achieving similar linearity performance with the simpler and more scalable bulk CMOS process.
Solution Approach 2:
The patent changes the voltage parameters applied to the well and body terminals to simulate the electrical characteristics of floating body devices. By switching between different voltage levels based on the switch state, the patent achieves reduced effective junction capacitances and improved linearity without requiring the complex SOI fabrication process.
3Manufacturing precision
If well and body bias voltages are switched to maximize reverse bias across junctions, then linearity is improved, but voltage breakdown risk increases
Solution Approach 1:
The patent uses dynamic switching of well and body voltage levels that are synchronized with the switch state. The control circuit applies the first well voltage level and first body voltage level when the switch is OFF, and switches to the second well voltage level and second body voltage level when the switch is ON. This dynamic coordination ensures maximum reverse bias for linearity improvement while preventing voltage breakdown by avoiding excessive reverse bias during the ON state.
Solution Approach 2:
The patent implements a control circuit that monitors the switch state and adjusts the well and body voltage levels accordingly. This feedback mechanism ensures that the voltage levels are optimized for linearity (maximum reverse bias) only when appropriate (OFF state), and are adjusted to safe levels during the ON state, thereby preventing voltage breakdown while maintaining improved linearity performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the linearity of RF switches by maximizing reverse bias across junctions without causing breakdown, improving the cost-performance tradeoff and maintaining voltage within tolerable ranges to reduce distortion.
Implementation Method 1
maximizing reverse bias across junctions without causing breakdown
Implementation Method 2
undesired junction capacitances can degrade the overall linearity of the circuit
Data Source
AI summary
RF transistors manufactured using a bulk CMOS process exhibit non-linear drain-body and source-body capacitances which degrade the linearity performance of the RF circuits implementing such transistors. The disclosed methods and devices address this issue and provide solutions based on implementing two or more bias voltages in accordance with the states of the transistors. Various exemplary RF circuits benefiting from the described methods and devices are also presented.