Bulk Substrate FET Integrated on CMOS SOI Wafer
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Solution Overview
Problem
Conventional methods face challenges in integrating high performance SOI CMOS devices with high voltage bulk substrate FETs on a single chip, particularly in applications requiring voltages between 12V-24V, such as automobiles and televisions, due to the difficulty in providing both high performance and high voltage capabilities simultaneously.
Innovation Solution
The integration of a semiconductor wafer with both SOI and bulk device regions, where an SOI FET is formed with an SOI gate stack and source/drain regions in the SOI device region, and a bulk FET is formed with a bulk gate stack and source/drain regions in the bulk device region, using a buried insulating layer to facilitate co-planar surfaces and shared processing steps, allowing for the creation of an integrated circuit that combines high performance and high voltage capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to integrate high performance SOI CMOS devices with high voltage bulk substrate FETs, then device performance can be maintained, but integration complexity and manufacturing difficulty increase significantly
Solution Approach 1:
The semiconductor wafer is divided into distinct SOI device regions and bulk device regions, allowing each region to be optimized for its specific function (high performance SOI CMOS or high voltage bulk FET) while maintaining a unified substrate structure. This segmentation enables independent device formation processes in each region without interfering with the other.
Solution Approach 2:
The buried insulating layer serves multiple functions: it acts as the foundation for SOI devices in the SOI regions, provides isolation for bulk devices in the bulk regions, and enables co-planar surface formation for both device types. This multi-functionality reduces the need for additional specialized structures.
2Reliability
If separate chips are used for high performance SOI CMOS devices and high voltage bulk devices, then each device type can be optimized independently, but manufacturing cost and assembly complexity increase
Solution Approach 1:
Both SOI CMOS devices and high voltage bulk FETs are integrated on a single semiconductor wafer with unified substrate and buried insulating layer. This merging allows simultaneous formation of both device types through shared processing steps, eliminating the need for separate chip fabrication, testing, and assembly operations.
Solution Approach 2:
The buried insulating layer and substrate serve as common foundations for both SOI and bulk device regions, enabling a single manufacturing process to produce both high performance and high voltage devices. This universal platform approach reduces per-device manufacturing costs compared to separate production lines.
3Adaptability or versatility
If high voltage bulk substrate FETs are added to SOI CMOS chip, then high voltage capability is achieved, but manufacturing precision requirements increase due to different process requirements
Solution Approach 1:
The wafer is segmented into SOI device regions and bulk device regions with distinct process integration sequences. SOI devices are formed first using standard SOI CMOS processes, then bulk FETs are added in subsequent steps. This segmentation allows each device type to receive its specific processing attention while maintaining overall process compatibility.
Solution Approach 2:
SOI devices are formed in advance before bulk FETs are integrated. The preliminary formation of SOI devices with their gate stacks and source/drain regions establishes a baseline structure that subsequent bulk FET processing must accommodate. This preliminary action allows process parameters to be optimized for SOI devices first, then adapted for bulk device integration.
Data Source
AI summary
An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.