Bulk RFIC Layer Transfer With Backside Silicidation and Deep Isolation

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Solution Overview

Problem

The high cost of semiconductor on insulator (SOI) wafers and handle substrates, such as HR-silicon or sapphire, limits the affordability and widespread adoption of high-performance radio frequency (RF) integrated circuits (RFICs) for mobile RF transceivers.

Innovation Solution

The use of bulk semiconductor wafers with a bulk layer transfer process and backside silicidation to create RFICs, which replaces expensive SOI wafers and handle substrates with more affordable bulk semiconductor materials, while maintaining or improving RF performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If SOI wafers and handle substrates are used to reduce parasitic capacitance and improve RF performance, then RF performance is improved, but manufacturing cost increases dramatically

Engineering Contradiction:

ImproveRF performanceVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent segments the semiconductor structure into distinct functional layers: the bulk semiconductor layer containing active devices, the deep trench isolation regions providing electrical isolation, and the handle substrate providing mechanical support. This segmentation allows each layer to be optimized independently, achieving SOI-like performance with bulk materials.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies deep trench isolation regions that extend through the entire bulk semiconductor layer to specific locations where electrical isolation is needed. This local application of isolation structures provides the necessary electrical separation to reduce parasitic capacitance and artificial harmonics only where required, rather than requiring expensive SOI wafers throughout the entire device.

Inventive Principle:

Principle #3Local quality

2Reliability

If deep trench isolation regions are formed extending through the bulk semiconductor layer, then electrical isolation is improved, but manufacturing complexity increases

Engineering Contradiction:

Improveelectrical isolationVSAvoidmanufacturing complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The deep trench isolation regions are formed early in the manufacturing process, before the active devices are fully constructed. This preliminary formation of isolation structures simplifies subsequent processing steps and allows for better integration with the overall device fabrication flow.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The deep trench isolation regions serve as intermediary structures that provide both electrical isolation and mechanical support functions. By combining multiple functions into a single structure, the overall device complexity is reduced while maintaining effective electrical isolation.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Ease of manufacture

If bulk semiconductor wafers are used instead of SOI wafers, then manufacturing cost is reduced, but parasitic capacitance reduction capability deteriorates

Engineering Contradiction:

Improvemanufacturing costVSAvoidparasitic capacitance reduction

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent extends the isolation approach from the traditional planar dimension into the vertical dimension by forming deep trench isolation regions that penetrate through the entire bulk semiconductor layer thickness. This three-dimensional isolation structure effectively reduces parasitic capacitance between active devices and the substrate, achieving performance comparable to SOI structures.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent uses composite material structures combining the bulk semiconductor layer with deep trench isolation regions filled with dielectric materials. This composite structure provides both the cost advantage of bulk semiconductors and the electrical isolation performance traditionally associated with expensive SOI wafers.

Inventive Principle:

Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the cost of RFIC production by utilizing inexpensive bulk semiconductor wafers, while achieving comparable RF performance to SOI-based devices through effective deep trench isolation and backside silicidation techniques.

Implementation Method 1

bulk layer transfer processing with backside silicidation

Methodology Applied

Scientific EffectSilicidation:

Data Source

PatentEP3688795B1Bulk layer transfer processing with backside silicidation

Publication Date: 2025.06.18 QUALCOMM INC

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AI summary

A radio frequency integrated circuit (RFIC) includes a bulk semiconductor die. The RFIC also includes a first active/passive device on a first-side of the bulk semiconductor die, and a first deep trench isolation region extending from the first-side to a second-side opposite the first-side of the bulk semiconductor die. The RFIC also includes a contact layer on the second-side of the bulk semiconductor die. The RFIC further includes a second-side dielectric layer on the contact layer. The first deep trench isolation region may extend through the contact layer and into the second-side dielectric layer.