Bulk Silicon FinFET Local Buried Isolation for Leakage Suppression
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Solution Overview
Problem
Conventional Bulk Silicon FinFET devices face issues such as short channel effects, large leakage, and poor impurity profile control, which are not adequately addressed by existing manufacturing methods, and they also suffer from self-heating and floating body effects similar to SOI FinFETs, making them less compatible with CMOS processes.
Innovation Solution
A method for manufacturing a Bulk Silicon FinFET involves forming a local buried isolation dielectric layer, creating a fin structure on a bulk silicon substrate, constructing a gate stack, and forming source/drain structures, which includes high energy ion implantation and annealing to improve isolation and impurity control, and is compatible with planar CMOS processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional Bulk Silicon FinFET structure is used, then manufacturing cost is reduced and heat dissipation is improved, but short channel effects cannot be suppressed and leakage is large
Solution Approach 1:
The device is segmented into distinct functional regions through the formation of a local buried isolation dielectric layer that divides the semiconductor substrate into isolated fin regions. This segmentation prevents leakage paths between fins while maintaining bulk silicon advantages, and enables independent control of each fin structure to suppress short channel effects.
Solution Approach 2:
The patent applies local quality by creating a buried isolation dielectric layer only in specific regions where fins are formed, rather than throughout the entire substrate. This localized isolation provides the necessary electrical separation to reduce leakage and improve SCE suppression precisely where needed, while preserving the bulk silicon substrate properties in other areas for heat dissipation and cost-effectiveness.
2Reliability
If a local buried isolation dielectric layer is formed, then short channel effects are suppressed and leakage is reduced, but manufacturing process complexity increases
Solution Approach 1:
The buried isolation dielectric layer is formed preliminarily before fin formation through ion implantation and annealing processes. This preliminary action establishes the isolation structure early in the manufacturing sequence, enabling subsequent fin formation and gate stack construction to proceed with improved impurity profile control without requiring additional complex isolation steps later in the process.
Solution Approach 2:
The patent utilizes parameter changes by controlling the ion implantation energy, dose, and annealing temperature to precisely control the depth and distribution of the buried isolation dielectric layer. By adjusting these parameters, the process achieves effective isolation and impurity profile control while maintaining compatibility with existing CMOS manufacturing processes, thereby limiting the increase in manufacturing complexity.
3Manufacturing precision
If high energy ion implantation and annealing are performed, then isolation is improved and impurity profile control is enhanced, but manufacturing time and energy consumption increase
Solution Approach 1:
The ion implantation and annealing processes are performed continuously in sequence without interrupting the manufacturing flow. The annealing step immediately follows ion implantation to activate the isolated dielectric layer and repair implantation damage in a continuous manner, minimizing idle time and maintaining manufacturing efficiency while achieving high isolation quality and impurity profile control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively suppresses short channel effects, reduces leakage, and improves impurity profile control, while being cost-effective and compatible with CMOS processes, overcoming the limitations of both Bulk Silicon and SOI FinFETs.
Implementation Method 1
implanting oxygen ions into the semiconductor substrate by means of high energy ion implantation
Implementation Method 2
performing high temperature annealing on the semiconductor substrate to form the local buried isolation dielectric layer
Data Source
AI summary
The present application discloses a method for manufacturing a semiconductor device, comprising: forming a local buried isolation dielectric layer in a semiconductor substrate; forming a fin in the semiconductor substrate and on top of the local buried isolation dielectric layer; forming a gate stack structure on a top surface and side surfaces of the fin; forming source/drain structures in portions of the fin which are on opposite sides of the gate stack structure; and performing metallization. A conventional quasi-planar top-down process is utilized in the present invention to achieve a good compatibility with the CMOS planar processes, easy integration, and suppression of short channel effects, which promotes the development of MOSFETs having reduced sizes.