Bulk Silicon Gate-All-Around Structure With Region-Specific Isolation Stress
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Solution Overview
Problem
Existing semiconductor devices face challenges in scaling and performance due to issues like short channel effects and punch-through, particularly when using bulk silicon substrates without silicon-on-insulator (SOI) technology.
Innovation Solution
The semiconductor device employs a substrate with distinct regions, featuring a laminate structure with alternately stacked sacrificial and active layers. Isolation insulating layers of different materials and thicknesses are formed on each region, allowing for varying stress applications to the active patterns, thereby enhancing mobility and reducing threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If bulk silicon substrates are used without SOI technology, then device fabrication is simpler, but short channel effects and punch-through occur
Solution Approach 1:
The substrate is divided into first and second regions with different isolation insulating layer configurations. The first region uses a first isolation insulating layer while the second region uses a second isolation insulating layer with different material composition or thickness, allowing independent optimization for each transistor type without requiring full SOI substrate complexity.
Solution Approach 2:
Different isolation insulating layers are applied to different regions of the substrate based on the specific requirements of NMOS and PMOS transistors. The first isolation insulating layer is optimized for NMOS devices while the second isolation insulating layer is optimized for PMOS devices, providing locally tailored electrical characteristics without uniform SOI structure.
2Device complexity
If uniform isolation insulating layers are used across all regions, then fabrication process is simpler, but carrier mobility and threshold voltage control are reduced
Solution Approach 1:
The isolation insulating layers are designed with different material compositions or thicknesses in different regions to apply varying stress to the active patterns. The first isolation insulating layer applies stress optimized for NMOS carrier mobility while the second isolation insulating layer applies stress optimized for PMOS carrier mobility, achieving region-specific performance enhancement.
Solution Approach 2:
The material composition, thickness, or both parameters of the isolation insulating layers are varied between the first and second regions to achieve different stress magnitudes and directions. This parameter variation allows independent optimization of carrier mobility and threshold voltage for different transistor types without increasing overall device complexity.
3Reliability
If different stress applications are implemented in different regions, then carrier mobility is improved, but fabrication process complexity increases
Solution Approach 1:
The semiconductor device is segmented into first and second regions with distinct isolation insulating layer configurations. This segmentation allows different stress applications in different regions while maintaining a systematic fabrication approach where each region can be processed independently according to its specific requirements.
Solution Approach 2:
The isolation insulating layers are configured with local quality variations - different materials, thicknesses, or compositions in different regions - to provide region-specific stress control. This approach achieves improved carrier mobility through localized optimization without requiring complex global fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses short channel effects and punch-through, improves carrier mobility, and enhances the overall performance of the semiconductor device without the need for SOI substrates.
Implementation Method 1
Isolation insulating layers of different materials and thicknesses are formed on each region, allowing for varying stress applications to the active patterns, thereby enhancing mobility and reducing threshold voltages
Data Source
AI summary
A semiconductor device includes a substrate with first and second regions separated from each other, a laminate structure including at least one sacrificial layer and at least one active layer alternately stacked on the substrate, a first isolation insulating layer on the laminate structure on the first region, a second isolation insulating layer on the laminate structure on the second region, the second isolation insulating layer having a same thickness as the first isolation insulating layer, a first upper active pattern spaced apart from the first isolation insulating layer, a first gate electrode surrounding at least a portion of the first upper active pattern, a second upper active pattern spaced apart from the second isolation insulating layer, and a second gate electrode surrounding at least a portion of the second upper active pattern, wherein top surfaces of the first and second isolation insulating layers are at different heights.