Bulk-Voltage Clock Buffer Control for Low-Jitter Distribution
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Solution Overview
Problem
Existing clock distribution circuitry faces challenges in accurately transmitting clock signals at low power with increasing speeds and miniaturization of semiconductor devices, requiring improved accuracy and reduced energy consumption.
Innovation Solution
The implementation of a clock distribution circuitry using a series of inverting buffers with control circuitry to generate variable control signals for adjusting duty cycle, slew, delay, and crossing points of clock signals, utilizing bulk voltage control to minimize noise and jitter, and employing a small number of independently controllable signals to reduce processing burden and size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock distribution circuitry operates at higher speeds with miniaturized semiconductor devices, then productivity and processing speed are improved, but energy consumption increases and accuracy deteriorates
Solution Approach 1:
The patent changes the control parameter from input voltage to bulk voltage of transistors. By controlling the bulk voltage instead of the input DC level, the circuit achieves better clock signal accuracy and reduced jitter while operating at high speeds. This parameter change allows for more efficient control of the clock distribution circuitry, addressing both the speed and energy consumption challenges.
2Productivity
If clock distribution circuitry operates at higher speeds, then productivity is improved, but manufacturing precision and signal accuracy deteriorate
Solution Approach 1:
The patent changes the control parameter from input voltage to bulk voltage of transistors. By controlling the bulk voltage instead of the input DC level, the circuit achieves better clock signal accuracy and reduced jitter while operating at high speeds. This parameter change allows for more efficient control of the clock distribution circuitry, addressing both the speed and energy consumption challenges.
Solution Approach 2:
The patent introduces bulk voltage control as an intermediary mechanism between the control signal and the clock signal generation. The bulk voltage acts as a mediator that influences the transistor operation without directly affecting the input signal path, thereby reducing noise transmission and improving signal accuracy at high operating speeds.
3Adaptability or versatility
If control signals are increased to adjust multiple clock signal properties, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent makes the bulk voltage control mechanism universal by applying it to multiple transistors across different buffer stages. A single bulk voltage control signal can simultaneously affect multiple clock signal properties (duty cycle, slew rate, delay) across the entire clock distribution network, reducing the need for separate control signals for each parameter and thereby simplifying the overall circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables precise adjustments to clock signal properties, reducing jitter and power consumption while maintaining accuracy, allowing for calibration and compensation for voltage or temperature variations using only four independently controllable control signals.
Implementation Method 1
the first buffers each comprise a pull-up circuit comprising one or more pull-up transistors connected for bulk-voltage control by the first control signal and a pull-down circuit comprising one or more pull-down transistors connected for bulk-voltage control by the second control signal
Data Source
AI summary
Clock distribution circuitry comprising: a plurality of first buffers and second buffers, the first and second buffers being inverting buffers; and control circuitry configured to generate first, second, third and fourth control signals for bulk-voltage control of transistors of the buffers, the control circuitry configured to control at least one of the first to fourth control signals as a variable signal.