Bump Array Reinforcement for Semiconductor Device Thermal Stress
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Solution Overview
Problem
Semiconductor devices experience connection failures due to thermal stress on bumps caused by differences in thermal expansion coefficients between the wiring substrate and mounting board, particularly at positions farthest from the center of the chip, leading to premature bump fracture and reduced device lifetime.
Innovation Solution
A semiconductor device with a reinforcing structure for the bump array located at positions farthest from the center of the chip, including the use of dummy bumps, shifting the bump arrangement, or forming larger bumps at these positions to alleviate stress concentration, thereby enhancing the durability of the bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the semiconductor chip is mounted offset from the center of the wiring substrate to ensure wire bonding space, then wire bonding accessibility is improved, but thermal stress on bumps increases due to structural asymmetry
Solution Approach 1:
The patent applies asymmetry by intentionally designing an asymmetric bump arrangement where the bump array is shifted relative to the chip center in the opposite direction of the chip offset. This creates a counterbalancing asymmetric structure that compensates for the stress concentration caused by the chip's asymmetric mounting position, thereby reducing thermal stress on bumps while maintaining wire bonding accessibility.
2Strength
If bump size is increased at four corners to enhance connection strength, then bump fracture resistance at corners is improved, but device complexity increases due to non-uniform bump configuration
Solution Approach 1:
The patent applies local quality by varying the bump pitch (spacing) in different regions of the bump array rather than using a uniform configuration. Specifically, the pitch is adjusted in the direction of chip offset to create locally optimized stress distribution. This provides enhanced connection strength where needed while maintaining a relatively simple overall bump arrangement that does not significantly increase device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reinforcing structure effectively relaxes stress concentration on specific bumps, prolonging their lifetime and improving the overall reliability of the semiconductor device without requiring significant changes to the bump mounting surface area or package size.
Implementation Method 1
thermal stress is applied to bumps due to a difference in thermal expansion coefficient between a wiring substrate and the mounting board
Implementation Method 2
greater thermal stress is applied to a bump array located at a farther position from the center of the wiring substrate in the chip shift direction due to asymmetry of the structure of the device
Data Source
AI summary
A ball grid array semiconductor device has a wiring substrate (2), a semiconductor chip (6) disposed on one surface side of the wiring substrate, and a bump arrangement (5) as external terminals disposed on a surface side, opposite to the one surface side, of the wiring substrate. The semiconductor chip is mounted so that the center of the semiconductor chip is shifted from the center of the semiconductor device by one pitch or more of the bump arrangement, and the bump arrangement has a reinforcing structure (5-2) for a bump array located at a position farthest from the center of the semiconductor device in a shift direction of the semiconductor chip.