Bump Bond Interconnect Layout for Front-Side Power Chip Current Handling

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Solution Overview

Problem

The fabrication of semiconductor power devices requires extensive processing to eliminate series resistance, leading to increased costs and complexity due to the need for metal deposition on both sides of the device, including backside contacts, which complicates current handling and increases manufacturing expenses.

Innovation Solution

The use of bump bonds as interconnects between metal lines and between the semiconductor device and the lead-frame eliminates the need for backside contacts, allowing for a simpler manufacturing process by distributing current and reducing the requirement for low resistance substrates, thereby reducing processing steps and costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If metal deposition is performed on both front and back sides of the semiconductor device to handle high current densities, then current carrying capability is improved, but device complexity and manufacturing cost increase due to extensive processing steps

Engineering Contradiction:
Improvecurrent carrying capabilityVSAvoidprocessing steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the backside contact requirement by implementing front-side-only metal deposition. The bump bonds are formed exclusively on the front side of the semiconductor device, eliminating the need for backside metal deposition and associated processing steps while maintaining current carrying capability through the lead-frame integration

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The bump bonds serve multiple functions: they act as current carrying conductors, provide mechanical bonding between the semiconductor device and lead-frame, and serve as interconnects between separate metal lines. This multi-functionality eliminates the need for separate backside contact structures

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If backside contacts are used to handle current, then current handling is improved, but manufacturing cost increases due to extensive processing to eliminate series resistance

Engineering Contradiction:
Improvecurrent handlingVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent removes the backside contact processing step entirely by forming all current handling structures on the front side. The metal lines and bump bonds are deposited and formed only on the front surface, eliminating the need for backside contact fabrication and series resistance elimination processing

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of using backside contacts as conventionally done, the patent inverts the approach by implementing all current handling and bonding structures on the front side only, reversing the traditional front-side device/back-side contact architecture

Inventive Principle:
Principle #13The other way round (Inversion)

3Reliability

If extensive processing is performed to eliminate series resistance, then current handling performance is improved, but manufacturing time and cost increase

Engineering Contradiction:
Improvecurrent handling performanceVSAvoidmanufacturing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts and eliminates the series resistance elimination processing step by designing a structure where series resistance is inherently minimized through the front-side-only metal deposition and direct bump bond formation, removing the need for extensive additional processing

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The metal lines and bump bonds are formed in advance during the front-side processing sequence, incorporating current handling functionality into the primary fabrication steps rather than requiring separate subsequent processing to address series resistance

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3146561B1Semiconductor device with bump bonds formed as metal line interconnects
Publication Date: 2024.03.20 MICROCHIP TECHNOLOGY INC
  • EP3146561B1 patent drawingFigure 1A~1C
  • EP3146561B1 patent drawingFigure 2A~2B
  • EP3146561B1 patent drawingFigure 3~4

AI summary

A semiconductor power chip has a semiconductor power device formed on a semiconductor die; wherein the semiconductor power device comprises an array of conductive contact elements; a passivation layer formed over the plurality of conductive contact elements, the passivation layer comprising passivation openings over a plurality of the conductive contact elements; and an array of conductive bumps including one or more interconnection bumps, wherein each interconnection bump is formed over the passivation layer and extends into at least two of the passivation openings and into contact with at least two underlying conductive contact elements to thereby provide a conductive coupling between the at least two underlying conductive contact elements.