Semiconductor Bump Coplanarity Using Recessed Dummy Bump Pads
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Solution Overview
Problem
In semiconductor packages, the height differences between active and dummy bumps can lead to either non-joints (opens) or smashed joints during flip-chip bonding, resulting in reliability and yield issues due to the formation of unwanted electrical shorts.
Innovation Solution
A process is developed to create recessed regions in the passivation layer using a leaky-chrome photolithography process, allowing the dummy bumps to be formed on these recessed regions, which helps in achieving a predetermined height range for both active and dummy bumps, thereby improving coplanarity and reducing the likelihood of non-joints and smashed joints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the height of conductive pillars is increased to ensure connection, then connection reliability is improved, but taller pillars may be crushed against conductive structures resulting in smashed joints
Solution Approach 1:
The patent applies parameter changes by modifying the height parameter of conductive pillars to fall within a specific range (5-15 micrometers). This parameter optimization ensures that pillars are tall enough to reliably connect to conductive structures while being short enough to avoid being crushed during bonding, thus resolving the contradiction between connection reliability and joint quality.
2Manufacturing precision
If the height of conductive pillars is decreased to avoid crushing, then joint quality is improved, but shorter pillars may not connect to conductive structures resulting in opens
Solution Approach 1:
The patent establishes a minimum height parameter of 5 micrometers for conductive pillars to ensure they are tall enough to reliably connect to conductive structures. This parameter setting prevents opens while maintaining joint quality, resolving the contradiction between connection reliability and joint quality.
3Ease of manufacture
If dummy bumps are formed at the same level as active bumps, then manufacturing is simplified, but height differences cause non-joints or smashed joints during flip-chip bonding
Solution Approach 1:
The patent applies local quality by creating recessed regions specifically under dummy bumps, while leaving active bump areas unchanged. This localized modification allows dummy bumps to be formed at a lower level (improving bonding reliability) while maintaining the simplicity of the overall manufacturing process. The recessed regions are selectively formed only where dummy bumps are located, preserving manufacturing ease while solving the bonding reliability issue.
4Manufacturing precision
If recessed regions are created for dummy bumps, then coplanarity is improved, but additional manufacturing steps are required
Solution Approach 1:
The patent applies preliminary action by forming recessed regions in the passivation layer before forming the conductive pillars and dummy bumps. This preliminary preparation ensures that when dummy bumps are formed, they naturally sit at the correct lower level, achieving improved coplanarity without requiring additional complex steps during the bump formation process itself. The recessed regions are prepared in advance, simplifying the overall process despite the added initial step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the coplanarity between active and dummy bumps, reducing the probability of yield and reliability issues by ensuring that the bumps are within an acceptable height range, thus facilitating effective flip-chip bonding without causing electrical shorts.
Implementation Method 1
exposing the polyimide layer using a reticle including a first region configured for a full exposure and a second region configured for a partial exposure
Data Source
AI summary
Improved bump coplanarity for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, when openings in a passivation layer of a semiconductor device are formed to expose surfaces of bond pads, additional openings may also be formed in the passivation layer. The additional openings may have depths shallower than the openings extending to the surfaces of bond pads by leveraging partial exposures to the passivation layer using a leaky chrome process. Subsequently, when active bumps (pillars) are formed on the exposed surfaces of bond pads, dummy bumps (pillars) may be formed on recessed surfaces of the additional openings such that differences in heights above the surface of the passivation between the active bumps and the dummy bumps are reduced to improve coplanarity.