Ni/Au Bump Height Control Using Sidewall Barrier Mask Transfer
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Solution Overview
Problem
The nickel/gold (Ni/Au) bumping process in integrated circuit packaging often results in the Ni/Au bump extending vertically over the upper surface of the second dielectric layer, leading to reduced bondability with transparent screen panels or carrier substrates due to seams or voids, which negatively impacts yield during bulk manufacture and packaging.
Innovation Solution
A mask transfer method is employed, involving the formation of a sidewall barrier structure and a hardmask layer to control the height of the bumping structure, preventing over-plating and ensuring the upper bumping structure does not extend vertically over the second dielectric layer, thereby improving bondability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the Ni/Au bumping process is performed without height control, then the bump structure is formed, but the bump extends vertically over the second dielectric layer causing seams and voids that reduce bondability
Solution Approach 1:
A sidewall barrier structure is formed along the sidewalls of the opening in the second dielectric layer before the bumping process. This preliminary structure prevents the Ni/Au bump material from extending vertically over the second dielectric layer during plating, thereby preventing seam and void formation and ensuring good bondability from the outset
Solution Approach 2:
The sidewall barrier structure acts as an intermediary element between the bump material and the second dielectric layer. It provides a physical barrier that mediates the interaction between the plating process and the dielectric layer, preventing direct contact and vertical extension of the bump material over the dielectric surface
2Quantity of substance
If the bumping process allows vertical extension, then complete coverage is achieved, but seams and voids form reducing manufacturing yield
Solution Approach 1:
The sidewall barrier structure provides localized protection at the critical interface between the bump and second dielectric layer. The barrier is applied specifically where needed - along the sidewalls of the opening - to prevent vertical extension, while allowing the bump to maintain adequate coverage over the conductive pad area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the bondability of the integrated circuit to transparent screen panels and carrier substrates by preventing the formation of 'fence' structures that cause seams and voids, thereby improving yield and reducing damage during bonding.
Implementation Method 1
An upper portion of the masking layer is removed, such that a lower portion of the masking layer is disposed in the first opening
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first dielectric structure having first inner sidewalls over an interlayer dielectric (ILD) structure. A second dielectric structure is over the first dielectric structure, where the first inner sidewalls are between second inner sidewalls of the second dielectric structure. A sidewall barrier structure is over the first dielectric structure and extends vertically along the second inner sidewalls. A lower bumping structure is between the second inner sidewalls and extends vertically along the first inner sidewalls and vertically along third inner sidewalls of the sidewall barrier structure. An upper bumping structure is over both the lower bumping structure and the sidewall barrier structure and between the second inner sidewalls, where an uppermost point of the upper bumping structure is at or below an uppermost point of the second dielectric structure.