Semiconductor Bump Layout Around Lens Material for Wafer Bonding

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Solution Overview

Problem

Bonding of semiconductor chips is not performed easily due to the presence of lens materials on the light collection surface, which complicates the formation of bumps and alignment, leading to low bonding efficiency and increased heat load in existing methods.

Innovation Solution

A semiconductor device with bumps on a first semiconductor substrate where the distance between the bump and the lens material is greater than twice the bump's diameter, allowing for easy bonding by forming the lens material in a region other than the bumps, and a manufacturing method that includes forming bumps and lens material with specific spacing to facilitate efficient chip bonding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If lens material is formed on the entire light collection surface including peripheral circuit region, then light collection efficiency is improved, but bump formation precision deteriorates due to increased opening depth

Engineering Contradiction:
Improvelight collection efficiencyVSAvoidbump formation precision
Core Design Contradiction:
Use of energy by moving objectVSManufacturing precision

Solution Approach 1:

The light collection surface is segmented into pixel region and peripheral circuit region. The lens material is formed only in the pixel region, while the peripheral circuit region remains exposed for bump formation. This segmentation allows the lens material to cover areas where it is needed for light collection while leaving areas where it would interfere with manufacturing processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The lens material coverage is made non-uniform across the light collection surface. Instead of covering the entire surface, the lens material is applied selectively only to the pixel region, creating local quality differences that optimize both light collection in the pixel region and manufacturing accessibility in the peripheral circuit region.

Inventive Principle:
Principle #3Local quality

2Measurement precision

If chip-on-chip bonding method is used, then alignment precision is maintained, but bonding efficiency deteriorates due to low productivity

Engineering Contradiction:
Improvealignment precisionVSAvoidbonding efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

Multiple chip bonding operations are merged into a single wafer-level bonding process. Instead of bonding chips individually in sequence, the invention enables simultaneous bonding of multiple chips to a wafer, combining what would be separate operations into one efficient process that maintains alignment precision while dramatically improving productivity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The bonding process transitions from a one-dimensional sequential chip-by-chip approach to a two-dimensional wafer-level parallel processing approach. By utilizing the wafer surface area and arranging multiple chips in a matrix, the process exploits an additional spatial dimension to enable simultaneous bonding operations.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Measurement precision

If multiple second semiconductor chips are bonded one by one to semiconductor wafer, then alignment precision is maintained, but bonding time increases in proportion to number of chips

Engineering Contradiction:
Improvealignment precisionVSAvoidbonding time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

Alignment marks are pre-formed on the semiconductor wafer before the bonding process. This preliminary action allows for rapid alignment of multiple chips during bonding, eliminating the need for time-consuming alignment procedures for each individual chip and enabling parallel processing of multiple chips simultaneously.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The alignment mark pattern is copied across the entire wafer surface, allowing each chip to be aligned using the same reference pattern. This copying approach enables consistent alignment precision across multiple chips while reducing the complexity of the alignment process, as the same alignment procedure can be applied to all chips in parallel.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS11862656B2Semiconductor device and manufacturing method, and electronic appliance
Publication Date: 2024.01.02 SONY GROUP CORP
  • US11862656B2 patent drawing
  • US11862656B2 patent drawing
  • US11862656B2 patent drawing

AI summary

There is provided a semiconductor device including: a plurality of bumps on a first semiconductor substrate; and a lens material in a region other than the plurality of bumps on the first semiconductor substrate, wherein a distance between a side of a bump closest to the lens material and a side of the lens material closest to the bump is greater than twice a diameter of the bump closest to the lens material, and wherein the distance between the side of the bump closest to the lens material and the side of the lens material closest to the bump is greater a minimum pitch of the bumps.