Bump-on-Trace Interconnects with Controlled Solder Wetting

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Solution Overview

Problem

Conventional bump-on-trace interconnects in flip-chip packaging face issues with electrical shorts and stress-induced delamination due to excessive solder joint size and full-height sidewall wetting, which leads to increased thermal stress and reduced reliability.

Innovation Solution

The improved bump-on-trace interconnect structure limits solder wetting to the bonding surface of the conductive metal pillar and predominantly the top surface of the metal line trace, with controlled solder joint size and minimal sidewall wetting, using copper or copper-based pillars and a metal oxide layer to enhance adhesion and reduce stress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If full-height sidewall wetting is used in conventional bump-on-trace interconnects, then solder joint strength is improved, but thermal stress and delamination increase

Engineering Contradiction:
Improvesolder joint strengthVSAvoidthermal stress resistance
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The patent applies local quality by differentiating the wetting behavior at different locations of the metal line trace. Solder is allowed to wet the top surface fully for strong bonding, but wetting on the sidewalls is limited to a controlled height portion only, creating localized differences in solder adhesion that balance strength and stress resistance

Inventive Principle:
Principle #3Local quality

2Reliability

If excessive solder joint size is used, then electrical connection reliability is improved, but electrical shorts between adjacent interconnects increase

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidelectrical shorts
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The invention uses local quality to create non-uniform solder distribution: the solder joint has adequate width and volume on the top surface to ensure reliable electrical connection, but the solder height on sidewalls is deliberately limited. This localized control prevents excessive solder from bridging to adjacent interconnects while maintaining sufficient bonding area

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent transitions from controlling solder joint size in two dimensions (width and height) to three dimensions by introducing vertical dimension control through partial sidewall wetting. By limiting solder wetting to only a portion of the sidewall height rather than full-height wetting, the solution creates a three-dimensional solder joint geometry that reduces short risk while maintaining connection reliability

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Strength

If full-height sidewall wetting is used, then solder joint adhesion is improved, but spacing between adjacent solder joints must be increased

Engineering Contradiction:
Improvesolder joint adhesionVSAvoidspacing between solder joints
Core Design Contradiction:
StrengthVSLength of moving object

Solution Approach 1:

The patent applies local quality by creating heterogeneous wetting zones: the top surface of the metal line trace receives full solder wetting for maximum adhesion, while the sidewalls receive limited wetting only up to a controlled height. This localized approach concentrates adhesion strength where needed (at the bonding interface) while reducing solder volume that would otherwise require larger spacing to prevent bridging

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces the likelihood of electrical shorts, increases spacing between solder joints, and decreases thermally induced stress, enhancing the reliability and robustness of the packaging assembly by minimizing delamination and peeling defects.

Implementation Method 1

using copper or copper-based pillars and a metal oxide layer to enhance adhesion and reduce stress

Methodology Applied
Scientific EffectAdhesion: Adhesive

Implementation Method 2

A solder joint joins the conductive metal pillar and the metal line trace. The wetting of the solder joint during the solder joint reflow process is controlled

Methodology Applied
Scientific EffectSoldering: Soldering

Data Source

PatentUS9917035B2Bump-on-trace interconnection structure for flip-chip packages
Publication Date: 2018.03.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9917035B2 patent drawing
  • US9917035B2 patent drawing
  • US9917035B2 patent drawing

AI summary

A bump-on-trace interconnection structure utilizing a lower volume solder joint for joining a conductive metal pillar and a metal line trace includes a conductive metal pillar having a bonding surface having a width WP and a metal line trace, provided on a package substrate, having a top surface with a width WT, where WP is greater than WT. The solder joint is bonded to the bonding surface by wetting across the width WP and bonded predominantly only to the top surface of the metal line trace by wetting predominantly only to the top surface across the width WT.