T-Shaped Bump Pad Layout for Fine-Pitch Package Bonding
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Solution Overview
Problem
The rapid miniaturization and multifunctionalization of electronic devices require semiconductor chips with fine pitch connection terminals and micro-sized electrode pads, but the manufacturing of semiconductor packages faces challenges such as peeling defects between bump pads and protective layers, which affect reliability and productivity.
Innovation Solution
The semiconductor package design includes a T-shaped bump pad with a metal seed layer and undercuts, surrounded by an insulating layer, to enhance bonding strength and reduce peeling defects, featuring a redistribution layer structure with tapered inverted trapezoidal vias and multiple metal wiring layers for efficient electrical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If micro-sized electrode pads are used to achieve miniaturization, then the semiconductor chip capacity increases, but peeling defects occur between bump pads and protective layers
Solution Approach 1:
The bump pad is designed with an asymmetric T-shaped cross-section where the upper structure width is greater than the lower structure width. This asymmetric geometry creates mechanical interlocking with the protective layer, preventing peeling defects while enabling miniaturization of the semiconductor chip.
Solution Approach 2:
The invention transitions from a conventional two-dimensional pad structure to a three-dimensional T-shaped structure with vertical depth components. The first and second undercuts extend in different directions (orthogonally), adding dimensional complexity that enhances bonding strength without increasing the chip's planar footprint.
2Productivity
If fine pitch connection terminals are implemented, then more connection points are available, but manufacturing precision requirements increase
Solution Approach 1:
The T-shaped bump pad structure with undercuts is formed in advance before final assembly. This preliminary formation of the asymmetric geometry provides built-in alignment features that guide subsequent manufacturing steps, reducing the precision requirements for fine pitch connection terminal implementation.
Data Source
AI summary
A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower structure.