Semiconductor Bump Structures with Passivation Spacer Etch Barrier
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Solution Overview
Problem
In semiconductor packages, over-etching of seed metal layers during bump fabrication can lead to undercut regions, reducing contact areas and increasing contact resistance, which is particularly problematic as semiconductor chips become more integrated and scaled down.
Innovation Solution
A bump structure featuring a metal post with a cylindrical shape and a passivation spacer on its sidewall, where the passivation spacer acts as an etch barrier to prevent undercut formation, and a metal pattern with a protrusion extending from the sidewall of the metal post, ensuring reliable electrical connection and adhesive strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the wet etch time is increased to completely remove the seed metal layer, then the seed metal layer is fully removed, but undercut regions are formed under the bumps causing failures
Solution Approach 1:
A protective layer is formed on the sidewalls of the bump structure before the wet etch process. This preliminary protective action prevents the etchant from attacking the metal layer at the interface, allowing complete removal of the seed metal layer without forming undercut regions that would compromise bump integrity.
Solution Approach 2:
The protective layer acts as an intermediary between the etchant and the metal layer. It selectively protects the sidewalls during the wet etch process, enabling the etchant to remove the seed metal layer completely while preventing lateral etching that would create undercut regions and reduce contact area.
2Manufacturing precision
If the wet etch time is increased to completely remove the seed metal layer, then the seed metal layer is fully removed, but the contact area between bumps and underlying layer is reduced increasing contact resistance
Solution Approach 1:
The protective layer is deposited on the sidewalls before the wet etch process, establishing a barrier that prevents etchant access to the metal-underlying layer interface. This allows extended etch time for complete seed metal removal while maintaining the original contact area geometry, thereby preventing increase in contact resistance.
Solution Approach 2:
The protective layer serves as an intermediary barrier during etching, mediating between the aggressive etchant and the metal layer. It enables complete removal of the seed metal layer through prolonged etching while preventing the formation of undercut regions that would reduce the contact area and increase contact resistance.
3Productivity
If the semiconductor chips are scaled down for higher integration, then the integration density is increased, but the sizes and pitches of the bumps are reduced making them more sensitive to over-etching
Solution Approach 1:
The protective layer is formed on the sidewalls of scaled-down bumps before the wet etch process. This preliminary protection is especially critical for miniaturized bumps where even minor undercut formation represents a larger proportion of the total bump dimension, enabling precise control of bump dimensions while achieving complete seed metal removal.
Solution Approach 2:
The protective layer acts as an intermediary that shields the scaled-down bump structures during etching. For miniaturized bumps with reduced sizes and pitches, this protective barrier prevents disproportionate undercut formation, maintaining manufacturing precision and dimensional control even as integration density increases.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents undercut regions and maintains contact area integrity, reducing contact resistance and enhancing the reliability of semiconductor packages, even as semiconductor chips are further integrated and miniaturized.
Implementation Method 1
the passivation spacer acts as an etch barrier to prevent undercut formation
Implementation Method 2
a metal material may be introduced into the bumps to electrically connect the semiconductor chips to each other
Data Source
AI summary
The bump structure includes a metal pattern disposed on an electrode pad to have a vertical sidewall and a recessed region surrounded by the vertical sidewalls, a metal post including a lower portion inserted into the recessed region and a protruded portion upwardly extending from the lower portion, and a passivation spacer on a sidewall of the metal post. The metal post is electrically connected to the electrode pad.