Bumped Substrate Flatness Control via Multi-Stage Reflow
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Solution Overview
Problem
Wafer warpage during the wafer level bumping process leads to unevenness in bump height, causing open circuits and requiring reworking or scrapping of electronic component assemblies.
Innovation Solution
A method to optimize the bumped substrate design by adjusting the bump layer design to reduce delta bow post reflow, involving forming, reflowing, measuring, and iteratively adjusting the bump layer to ensure a flat substrate with acceptable delta bow, using a stack of adhesion, current-carrying, and solder-wettable layers to manage stress changes during reflow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wafer level bumping process is performed, then electrical interconnections are formed, but substrate warpage causes uneven bump height leading to open circuits
Solution Approach 1:
The patent applies preliminary action by performing a pre-reflow heating step before the main reflow process. This pre-reflow step pre-conditiones the substrate and bump layer, reducing thermal stress and preventing excessive warpage during the subsequent reflow process, thereby maintaining bump height uniformity and preventing open circuits
Solution Approach 2:
The patent applies parameter changes by optimizing the heating rate, peak temperature, and dwell time of the reflow process. By carefully controlling these thermal parameters and using a multi-stage heating approach (pre-reflow at lower temperature followed by main reflow), the patent reduces thermal stress-induced warpage while still achieving proper solder reflow and electrical interconnections
2Reliability
If reflow process is used to form interconnections, then electrical connections are created, but substrate warpage increases causing transistor shifts
Solution Approach 1:
The pre-reflow heating step serves as preliminary action that activates the solder material and reduces thermal gradients in the substrate before the main reflow process. This preliminary conditioning minimizes sudden thermal expansion and warpage during the main reflow, maintaining substrate flatness while achieving reliable electrical connections
Solution Approach 2:
The patent applies dynamics by using a multi-stage, time-dependent heating process rather than a single static temperature step. The dynamic heating profile (gradual pre-heating followed by controlled peak temperature) allows the substrate and bump layer to adapt thermally, reducing stress accumulation and warpage while ensuring complete solder reflow
3Ease of manufacture
If delta bow is not controlled, then manufacturing is simpler, but open circuits and reworking occur
Solution Approach 1:
The patent applies parameter changes by establishing specific reflow process parameters (heating rate, peak temperature, dwell time) and a multi-stage temperature profile. These controlled parameter changes ensure delta bow remains within acceptable limits, preventing open circuits and reworking while maintaining a relatively simple manufacturing process
Solution Approach 2:
The patent applies feedback by measuring delta bow after the reflow process and using this information to adjust and optimize the reflow profile for subsequent production batches. This feedback loop ensures consistent substrate flatness and high assembly reliability while maintaining manufacturing efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Ensures reliable electrical interconnections by maintaining a flat substrate, preventing transistor shifts and open circuits associated with warped substrates, and enabling mass production of reliable flip chip interconnections.
Implementation Method 1
manage stress changes during reflow
Implementation Method 2
stack of adhesion, current-carrying, and solder-wettable layers
Implementation Method 3
solder-wettable layers to manage stress changes during reflow
Data Source
AI summary
A bumped substrate is optimized to be flat post reflow. By producing the bumped substrate to be flat post reflow, device reliability is assured. More particularly, the transistor shift associated with warped substrates is avoided. Further, by producing a flat bumped substrate post reflow, reliability in the flip chip interconnections is assured as compared to the undesirable open circuits associated with warped substrates.