Bumpless Build-Up Layer Interposer for Stacked Microelectronics
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Solution Overview
Problem
Microelectronic device packages face challenges in minimizing space as device sizes shrink, requiring innovative designs to efficiently stack components while managing thermal expansion and interconnection density.
Innovation Solution
The use of a bumpless build-up layer (BBUL) design incorporating an interposer, such as a through-silicon via interposer, which facilitates stacked microelectronic components by creating a high-interconnection density without the need for traditional bumps, using conductive vias and dielectric layers to connect microelectronic dice and external interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional bump-based interconnection methods are used, then mechanical strength and electrical connection are achieved, but space occupation increases and thermal expansion mismatches occur
Solution Approach 1:
The patent removes the traditional bump structure from the interconnection system. By extracting the bump element entirely and replacing it with a planarized build-up layer containing conductive vias, the design eliminates the space occupation and thermal expansion issues associated with bumps while maintaining interconnection functionality through alternative means
Solution Approach 2:
The patent introduces a build-up layer as an intermediary structure between the substrate and the stacked microelectronic components. This build-up layer serves as a mediator that provides both mechanical support and electrical interconnection through conductive vias, replacing the direct bump-to-bump connection while enabling planarization and thermal expansion management
2Volume of moving object
If stacked microelectronic components are implemented to minimize space, then volume efficiency improves, but thermal expansion mismatches and interconnection complexity increase
Solution Approach 1:
The patent transitions from vertical bump-based interconnection to a planar two-dimensional network of conductive vias within the build-up layer. This dimensional shift allows multiple interconnection paths to be established in the lateral plane, simplifying the stacking process while maintaining high interconnection density and enabling better thermal expansion management through the planar structure
3Volume of moving object
If bumpless build-up layer design is used, then space is minimized and thermal expansion mismatches are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates alignment features and reference structures during the build-up layer fabrication process. By establishing precise via locations and patterns in advance during the build-up construction, the design pre-configures the interconnection geometry to meet alignment requirements, thereby managing manufacturing precision demands through proactive design rather than reactive correction
Data Source
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AI summary
The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein an interposer, such as a through-silicon via interposer, may be used in a bumpless build-up layer package to facilitate stacked microelectronic components.