Bumpless Build-Up Layer Package With Pre-Stacked TSV Devices
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Solution Overview
Problem
Existing microelectronic device package designs face challenges in preventing warpage and yield losses due to solder ball bridging and non-contact opens, particularly when stacking microelectronic devices with through-silicon vias in a bumpless build-up layer configuration.
Innovation Solution
A microelectronic package design involving pre-stacked microelectronic devices with through-silicon vias, where a first microelectronic device is stacked with a second device using interconnects and underfill material, and a build-up layer is formed with conductive traces and dielectric layers, enhancing structural integrity and preventing warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If microelectronic devices are stacked with through-silicon vias in a bumpless build-up layer configuration, then device integration density is improved, but warpage and yield losses occur due to solder ball bridging and non-contact opens
Solution Approach 1:
The patent introduces an underfill material as an intermediary substance between the stacked microelectronic devices and the substrate. This underfill material fills the gaps and voids in the bumpless build-up layer configuration, providing mechanical support and preventing warpage while eliminating solder ball bridging and non-contact opens issues, thus maintaining both high device integration density and package reliability
2Device complexity
If a bumpless build-up layer configuration is used, then manufacturing complexity is reduced, but structural integrity and warpage prevention become problematic
Solution Approach 1:
The patent employs composite material structure by combining the bumpless build-up layer configuration with underfill material. The underfill material acts as a reinforcing composite that enhances the structural integrity of the package, preventing warpage and improving mechanical strength while maintaining the manufacturing simplicity advantages of the bumpless build-up layer approach
Data Source
AI summary
The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.