Bumpless Build-Up Microelectronic Package with Through-Silicon Vias
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Solution Overview
Problem
The microelectronic industry faces challenges in producing smaller and faster microelectronic packages with numerous conductive routes, which requires stringent design rules and multiple layers of dielectric material, leading to increased size and cost.
Innovation Solution
The implementation of a microelectronic package with a first bumpless build-up layer structure adjacent the active surface and a second bumpless build-up layer structure adjacent the back surface, utilizing through-silicon vias to redistribute conductive routes, reducing the need for extensive dielectric and conductive trace layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple layers of dielectric material and conductive traces are used to achieve proper routing to external interconnects, then the number of conductive routes is increased, but the package size and device complexity increase
Solution Approach 1:
The patent utilizes through-silicon vias (TSVs) to route signals vertically through the substrate, transitioning from planar routing to three-dimensional routing. This vertical dimension allows conductive routes to pass through the substrate thickness, enabling signal distribution to multiple layers without increasing lateral package size. The TSVs create vertical conductive pathways that connect different stacking levels, effectively using the Z-dimension to solve routing density issues.
Solution Approach 2:
The patent implements a stacked package architecture where multiple die layers are vertically nested within a compact footprint. Each die layer contains functional circuits and bonding pads, with TSVs providing inter-layer connectivity. This nesting approach allows multiple functional layers to be integrated within a small lateral area, increasing the effective number of conductive routes without proportionally increasing package size.
2Quantity of substance
If multiple layers of dielectric material and conductive traces are used to achieve proper routing to external interconnects, then the number of conductive routes is increased, but the number of manufacturing layers and design rules increase
Solution Approach 1:
The patent replaces multiple lateral dielectric layers with vertical TSV routing. Instead of creating numerous planar signal traces through thick dielectric stacks, the design uses through-silicon vias to punch vertical holes through the substrate, filling them with conductive material. This vertical routing approach reduces the number of lateral dielectric layers needed while maintaining high conductive route density.
Solution Approach 2:
The patent extracts the routing function from the planar dielectric trace layer and relocates it to vertical TSV structures. By separating the signal routing function into dedicated vertical via structures, the design simplifies the remaining dielectric layers, which no longer need to contain complex trace patterns. This extraction reduces the overall layer count and simplifies manufacturing.
3Quantity of substance
If a larger microelectronic device is used to accommodate numerous conductive routes, then routing capability is improved, but the package size increases
Solution Approach 1:
The patent transitions from two-dimensional planar routing to three-dimensional vertical routing using TSVs. This allows the device to maintain a small lateral footprint while achieving high routing capability through vertical signal pathways. The routing capacity scales with the number of TSVs that can be packed vertically, not with the lateral device area.
Solution Approach 2:
The patent employs thin-film deposition techniques to create the TSV conductive liners and fill materials. These thin film structures provide the necessary electrical connectivity with minimal lateral space requirements, enabling high-density routing within a compact device footprint.
Data Source
AI summary
A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes.