Bumpless Chip Package Conductive Channel Signal Path
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Solution Overview
Problem
Conventional bumpless chip packages face issues with signal transmission path length and chip edge cracking due to high operational temperatures and thermal expansion differences between the chip and panel-shaped components, affecting chip performance and longevity.
Innovation Solution
A bumpless chip package design incorporating a conductive channel that extends from the active surface of the chip to its side surface, electrically connecting chip pads to the panel-shaped component, formed through an electroplating process, which shortens the signal transmission path and mitigates edge cracking by managing thermal expansion differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional BGA package technology with flip chip bonding or wire bonding is used, then electrical connection between chip and package substrate is achieved, but signal transmission path becomes long resulting in signal transmission delays
Solution Approach 1:
The patent merges the chip body with the interconnection structure by fabricating the interconnection structure directly on the chip's active surface, eliminating the need for separate bonding processes. This integration shortens the signal transmission path from the chip pads through the interconnection structure to the contact pads, thereby improving signal transmission speed while reducing structural complexity.
Solution Approach 2:
The patent transitions from a conventional planar connection approach to a three-dimensional interconnection structure with multiple conductive layers stacked vertically. This dimensional change allows signals to travel through shorter vertical paths via conductive vias rather than long lateral paths, significantly reducing transmission delays.
2Loss of time
If multi-layered interconnection structure is fabricated on chip to eliminate bonding processes, then signal transmission path is shortened, but chip edge cracking occurs due to high operational temperature and thermal expansion difference
Solution Approach 1:
The patent applies different material properties to different regions of the chip package. Specifically, the coefficient of thermal expansion (CTE) of the interconnection structure is designed to match that of the chip substrate, while the surrounding package materials are selected to provide thermal management. This local quality matching prevents differential thermal stress at the chip edges during temperature cycling, eliminating cracking while maintaining the shortened signal path benefits.
3Adaptability or versatility
If high layout density package substrate is used to achieve high integration, then device functionality is improved, but signal transmission path length increases causing performance degradation
Solution Approach 1:
The patent utilizes a three-dimensional interconnection architecture with multiple stacked conductive layers and vertical vias. This allows signal routes to be optimized in the vertical dimension rather than being constrained to lateral paths on a two-dimensional plane. Even with high layout density requiring many interconnections, the vertical stacking enables shorter overall signal paths, maintaining high transmission speeds while supporting high device integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The conductive channel reduces signal transmission delays and prevents chip edge cracking, enhancing the package's electrical efficiency and extending the chip's lifespan by addressing thermal expansion issues.
Implementation Method 1
One end of the conductive channel is electrically connected to at least one of the chip pads and the other end of the conductive channel is electrically connected to the panel-shaped component
Implementation Method 2
formed through an electroplating process
Implementation Method 3
prevents the edge of the chip from cracking due to high operational temperature and the difference of coefficient of thermal expansion (CTE) between the chip and the panel-shaped component
Data Source
AI summary
A bumpless chip package including at least a panel-shaped component, a chip, an interconnection structure and a conductive channel is provided. The chip is disposed on the panel-shaped component. The chip has a plurality of chip pads disposed on an active surface of the chip. The interconnection structure is disposed on the panel-shaped component and the chip. The interconnection structure has an inner circuit and a plurality of contact pads. The contact pads are disposed on a contact surface of the interconnection structure. At lease one chip pad is connected electrically to at least one contact pad by the inner circuit. The conductive channel extends from the active surface of the chip to a side surface thereof adjacent to the active surface. One end of the conductive channel is electrically connected to at least one chip pad and the other end thereof is electrically connected to the panel-shaped component.