Bumpless Die-Package Interface for BBUL Fabrication

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Current methods for fabricating interfaces between embedded silicon dies and packaging assemblies require numerous processing steps, increasing manufacturing complexity and cost.

Innovation Solution

A bumpless interface approach is implemented, using a carrier structure with prepreg material and metal foils to form back-to-back die assemblies, where a dielectric layer and conductive paths are created to enable electrical coupling without bumps, simplifying the fabrication process and reducing steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional bump-based interface methods are used, then reliable electrical coupling is achieved, but manufacturing complexity and processing steps increase

Engineering Contradiction:

Improveelectrical coupling reliabilityVSAvoidfabrication process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The invention extracts and eliminates the bump structures from the traditional interface methodology. By removing the bump-based connection approach and replacing it with a planar conductive path through the substrate, the patent simplifies the fabrication process while maintaining electrical coupling reliability between stacked IC packages.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The invention segments the electrical connection path into distinct functional zones: pad regions on upper and lower packages, conductive paths through the substrate, and intermediate connection regions. This segmentation allows for simplified manufacturing while ensuring reliable electrical coupling at each interface point.

Inventive Principle:

Principle #1Segmentation

2Manufacturing precision

If numerous processing steps are used to create die-package interfaces, then precise electrical alignment is achieved, but manufacturing cost and time increase

Engineering Contradiction:

Improveelectrical alignment precisionVSAvoidmanufacturing throughput

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The substrate is pre-configured with conductive paths and pad regions before the IC packages are mounted. This preliminary preparation of the substrate's electrical infrastructure enables precise alignment to be achieved during package placement without requiring subsequent complex processing steps to create conductive pathways.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The substrate serves multiple functions simultaneously: it provides mechanical support for stacked packages, establishes electrical connections between packages, and defines alignment references through its pad and conductive path geometry. This multi-functionality reduces the need for separate processing steps for each function.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS9576909B2Bumpless die-package interface for bumpless build-up layer (BBUL)

Publication Date: 2017.02.21 INTEL CORP

AI summary

Embodiments of the present disclosure are directed towards bumpless interfaces to an embedded silicon die, in integrated circuit (IC) package assemblies. In one embodiment, a method includes forming a surrounding portion of dielectric material defining a cavity therein; placing at least one die in the cavity, the die including a contact; depositing a dielectric material on the die and the surrounding portion; etching the dielectric material to expose the contact; and depositing conductive material onto the contact. Other embodiments may be described and/or claimed.