Bumpless Fan-Out Chip Stacking Structure for High-Density Integration
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Solution Overview
Problem
Current three-dimensional packaging technologies, such as System-on-a-chip (SoC) and System-in-Package (SIP), face challenges in miniaturization due to the need for bonding wires and solder bumps, which increase package volume and are prone to thermal stress issues as more integrated circuits are added.
Innovation Solution
A bumpless fan-out chip stacking structure is developed, utilizing a substrate, dielectric layers, redistribution layers, via plugs, capping layers, and patterned conductive layers to electrically connect dies without bonding wires or solder bumps, allowing for vertical stacking and increased package density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding and flip chip technology are used to connect packaged chips, then electrical connection between chips is achieved, but additional space for bonding wires and bond pads is required, making it difficult to shrink package volume when more chips are integrated
Solution Approach 1:
The patent extracts and eliminates the bonding wires and solder bumps from the interconnection process. Instead of using traditional wire bonding or flip chip technology with solder bumps, the invention uses a bumpless fan-out wafer-level packaging approach where chips are interconnected through embedded conductors and redistribution layers within the package substrate itself, removing the need for separate bonding components and reducing overall package volume.
Solution Approach 2:
The patent transitions from two-dimensional planar interconnection (wire bonding on chip surfaces) to three-dimensional embedded interconnection (conductors routed through and within the package substrate layers). This allows signals to be routed in multiple dimensions through the substrate, enabling higher density integration without proportionally increasing package footprint or volume.
2Reliability
If flip chip technology with solder bumps is used to connect packaged chips, then electrical connection is achieved, but excessive thermal stress causes solder bumps to overflow or be damaged, leading to system failure
Solution Approach 1:
The patent removes solder bumps entirely from the interconnection process. Instead of using flip chip technology with solder bumps that are susceptible to thermal stress, the invention employs a bumpless wafer-level packaging approach where chips are bonded directly to the substrate using underfill adhesive, and interconnections are established through embedded conductors and redistribution layers, eliminating the thermal stress vulnerability of solder bumps.
Solution Approach 2:
The patent replaces the mechanical solder bump connection system with an embedded conductor system. Instead of relying on solder bumps to bridge electrical connections between chips and substrate, the invention routes signals through conductors embedded within the substrate layers, which are mechanically more robust and less susceptible to thermal stress and vibration damage.
3Adaptability or versatility
If SoC technology is used to integrate various devices into a single chip, then signal processing capabilities are improved, but costs and time increase steeply due to processing difficulty of critical dimension shrinkage
Solution Approach 1:
The patent divides the system into separate functional modules (chips) that can be manufactured independently using optimized processes for each function, then integrated at the wafer-level packaging stage. This allows each chip to be manufactured at its optimal process node without requiring the entire system to be fabricated at the smallest critical dimension, reducing manufacturing complexity and cost while maintaining high signal processing capabilities.
Solution Approach 2:
The patent creates a universal package substrate platform that can accommodate multiple different chip types and configurations. The embedded conductor pattern and redistribution layer structure serve multiple functions: providing electrical interconnections, enabling signal routing, and supporting various chip layouts. This universal platform reduces development time and manufacturing cost across different product variants.
Data Source
AI summary
A bumpless fan-out chip stacking structure includes a first die disposed on the substrate, a first dielectric layer conformally covering on the first die, a first RDL disposed on the first dielectric layer, a first via plug electrically connecting the first die to the first RDL, a first capping layer conformally covering on the first RDL, a second die attached on the first capping layer, a second dielectric layer conformally covering on the second die, a second RDL disposed on the second dielectric layer, a second via plug electrically connecting the second die to the second RDL, a second capping layer conformally covering on the second RDL, a patterned conductive layer disposed on the second capping layer and an interlayer connection structure electrically connecting the patterned conductive layer to the first RDL and the second RDL respectively.