Bundle Status Circuits for NAND Flash Defect Detection
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Solution Overview
Problem
Existing memory device detecting circuits face challenges in reducing processing time and identifying defect locations, particularly in NAND Flash arrays where open bit-line contacts increase defects, requiring efficient defect detection and redundancy analysis.
Innovation Solution
The implementation of a daisy chain configuration of bundle status circuits that reduces processing time by coupling each bundle status circuit to respective bundles in the buffer structure, allowing for faster detection and identification of defects, and utilizing control circuitry to execute cycles and count bundle status circuits indicating a fail status, enabling location and repair of defective storage elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple FBDUs corresponding to respective bit lines are connected in series to store fail bit information, then accurate counting of fail bit information for all bit lines is achieved, but time to process the FBDUs becomes significant
Solution Approach 1:
The patent segments the bit lines into multiple groups, with each FBDU responsible for a specific group rather than processing all bit lines sequentially. This segmentation allows parallel processing of fail bit detection across different groups, maintaining accurate counting while significantly reducing the total processing time by eliminating the sequential bottleneck.
2Quantity of substance
If FBDUs are used to detect fail bits, then the number of defects can be counted, but locations of defects are not known
Solution Approach 1:
The patent introduces an intermediary mapping mechanism that connects each FBDU to its corresponding bit line group. This mapping structure serves as an intermediary that preserves location information by maintaining the relationship between the detected fail bits and their original bit line positions, enabling both counting and location identification of defects.
3Reliability
If the number of defects exceeds ECC requirements, then errors cannot be fixed during read operation, but no mechanism is provided to proactively identify and mark bad blocks
Solution Approach 1:
The patent implements preliminary action by proactively detecting and counting fail bits during program or erase operations, before they become problematic during read operations. The system compares the counted fail bits against ECC thresholds and preemptively marks blocks as bad, preventing future read failures and ensuring data integrity before errors occur.
Data Source
AI summary
An integrated circuit memory includes a memory array, including a plurality of data lines. A buffer structure is coupled to the plurality of data lines, including a plurality of storage elements to store bit-level status values for the plurality of data lines. The memory includes logic to indicate bundle-level status values of corresponding bundles of storage elements in the buffer structure based on the bit-level status values of bits in the corresponding bundles. A plurality of bundle status circuits is arranged in a daisy chain and coupled to respective bundles in the buffer structure, producing an output of the daisy chain indicating detection of a bundle in the first status. Control circuitry executes cycles to determine the output of the daisy chain, each cycle clearing a bundle status circuit indicating the first status if the output indicates detection of a bundle in the first status in the cycle.