Buried 3D Capacitor Structure for Higher Capacitance Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As electronic devices become more compact and feature-dense, it is challenging to increase capacitance within a given area while maintaining or reducing the footprint of capacitors, especially in three-dimensional memory devices where memory cells and capacitors are formed closely together at smaller dimensions.
Innovation Solution
The design of 'buried, two-sided capacitors' with horizontal and vertical electrode orientations within the base material, where the upper electrode contacts vertically extending pillar regions and a horizontally extending lower electrode, allowing for increased capacitance without expanding the footprint, achieved by forming sacrificial material, removing it, and depositing conductive material within the base material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If capacitors are formed as conventional MOS capacitors or well capacitors above the base material, then the fabrication process is simplified, but the capacitance per unit area is limited and footprint cannot be reduced
Solution Approach 1:
The patent transitions from conventional planar capacitors to three-dimensional buried capacitors with electrodes extending vertically into the substrate. The gate electrode includes a lower portion extending horizontally within the substrate and an upper portion overlying the substrate surface, creating a multi-dimensional structure that increases capacitance per unit area by utilizing vertical space rather than only horizontal plane.
Solution Approach 2:
The buried capacitor structure embeds the lower electrode and associated structures within the substrate volume, nesting the capacitor components inside the base material rather than placing them all on the surface. This nesting approach allows the capacitor to occupy three-dimensional space within the substrate, increasing capacitance density without expanding the device footprint.
2Quantity of substance
If memory cells and capacitors are formed closer together at smaller dimensions, then packing density is improved, but it becomes increasingly difficult to increase capacitance within a given area
Solution Approach 1:
The gate electrode is segmented into distinct lower and upper portions that can be formed at different stages and with different materials. The lower electrode portion extends within the substrate while the upper portion overlies the surface, allowing independent optimization of each segment's dimensions and properties to achieve high capacitance density while maintaining manufacturability.
Solution Approach 2:
The patent introduces a sacrificial material that is temporarily placed within the substrate, then removed to create space for the lower electrode. This intermediary approach enables precise formation of the buried electrode structure without requiring direct patterning at the deepest substrate levels, thereby maintaining manufacturing precision while achieving high capacitance density.
3Area of stationary object
If the footprint of capacitors is reduced to optimize packing density, then area efficiency is improved, but the formation process becomes more complex
Solution Approach 1:
The sacrificial material is deposited and patterned beforehand to define the precise location and geometry of the lower electrode before the actual electrode formation. This preliminary action simplifies subsequent processing steps by pre-establishing the template for the buried capacitor structure, reducing overall process complexity despite the advanced three-dimensional configuration.
Solution Approach 2:
The formation of the buried capacitor is merged with the existing transistor fabrication process flow, using similar deposition and etching techniques. By combining the capacitor formation steps with the already-established manufacturing process, the patent reduces the addition of complex new process steps while achieving reduced footprint and high capacitance density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances capacitance efficiency per unit area, allowing for either increased capacitance within a given area or reduced area allocation for capacitors, optimizing packing density without increasing the footprint, and simplifies the formation process by reducing processing complexities.
Implementation Method 1
depositing conductive material within the base material
Implementation Method 2
depositing conductive material within the base material
Data Source
AI summary
An electronic device includes one or more capacitors adjacent to a base material. The one or more capacitors comprise at least one electrode extending horizontally within the base material, and additional electrodes extending vertically within the base material and contacting the at least one electrode. The at least one electrode is located below and isolated from an upper surface of the base material. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.