Buried Access Line Resistance Reduction in Memory Arrays
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Solution Overview
Problem
Existing memory arrays face challenges in reducing resistance along buried access lines, which affects performance and density, as memory cells farther from conductive vias experience higher resistance, limiting the number of cells that can be placed between vias.
Innovation Solution
The use of higher conductivity metal material directly against the tops of buried access lines and extending between pillars, forming pairs of buried and outer access lines, reduces resistance and enables more memory cells to be placed between conductive vias, improving array performance and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are placed farther from conductive vias to increase density, then circuit density improves, but electrical resistance along buried access lines increases
Solution Approach 1:
The access line is segmented into two parts: a buried access line extending from the via to beneath the pillars, and an outer access line extending above the pillars. This segmentation allows each segment to be optimized independently - the buried portion provides structural support while the outer portion provides low-resistance electrical connection, resolving the contradiction between density and resistance.
Solution Approach 2:
The solution transitions from a single-plane access line to a three-dimensional structure with both buried and outer components. The outer access line is positioned elevationally outward of the pillars, creating a vertical dimension that bypasses the high-resistance region, thereby reducing overall resistance while maintaining high density.
2Quantity of substance
If more memory cells are placed between conductive vias, then array density improves, but performance deteriorates due to higher resistance
Solution Approach 1:
By segmenting the access path into buried and outer components, the invention enables more memory cells to be placed between vias without sacrificing performance. The outer access line provides a low-resistance parallel path that compensates for the increased length and resistance of the buried access lines serving additional cells.
Solution Approach 2:
The access line system functions as a composite structure combining buried access lines (providing structural integration) with outer access lines (providing low-resistance electrical connection). This composite approach enables high density while maintaining performance by leveraging the complementary strengths of each component.
3Device complexity
If only buried access lines are used, then device complexity is reduced, but electrical resistance increases limiting density
Solution Approach 1:
The access line is divided into buried and outer segments, each serving a specific function. This segmentation allows the system to achieve low resistance and high density without substantially increasing complexity, as each segment can be formed using standard fabrication processes.
Solution Approach 2:
The outer access lines serve multiple functions: providing low-resistance electrical connection, enabling higher density, and potentially serving as interconnect layers for other circuit elements. This multi-functionality justifies the added structural complexity by delivering multiple benefits simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces electrical resistance along buried access lines, enhancing memory array performance and allowing for increased circuit density by enabling more memory cells to be placed between conductive vias.
Implementation Method 1
The crystallization temperature and the melting temperature are obtained by causing an electric current to flow through the heater material, thus heating the phase change material
Data Source
AI summary
An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. The pillars individually include a memory cell. Outer access lines are elevationally outward of the pillars and the buried access lines. The outer access lines are of higher electrical conductivity than the buried access lines. A plurality of conductive vias is spaced along and electrically couple pairs of individual of the buried and outer access lines. A plurality of the pillars is between immediately adjacent of the vias along the pairs. Electrically conductive metal material is directly against tops of the buried access lines and extends between the pillars along the individual buried access lines. Other embodiments, including method, are disclosed.