Buried Bias Pad Structure for Transistor Breakdown Voltage Control
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Solution Overview
Problem
Transient or uncontrolled voltage in the substrate beneath transistors in integrated circuits affects switching speed and introduces noise, limiting the breakdown voltage and operational life of integrated circuits.
Innovation Solution
Incorporating bias pads within the buried oxide layer, which are electrically connected to the substrate and transistors, allows for individual adjustment of bias voltage to each transistor, reducing leakage current and enhancing the breakdown voltage performance by regulating the electrical environment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the buried oxide layer is increased to improve breakdown voltage, then the operating voltage window and functional life are extended, but the manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent divides the single thick buried oxide layer into multiple thinner oxide layers separated by conductive interlayers. This segmentation allows each layer to be formed using standard thin oxide deposition processes while collectively achieving the desired breakdown voltage through the stacked structure, avoiding the need for single thick oxide formation which requires specialized processes.
Solution Approach 2:
The patent creates a composite structure combining multiple oxide layers with different dielectric properties and conductive interlayers. This composite approach enables tailored electrical characteristics where each material layer contributes specific properties, achieving high breakdown voltage while maintaining compatibility with existing manufacturing processes.
2Reliability
If bias pads are integrated within the buried oxide layer to regulate electrical environment, then leakage current is reduced and breakdown voltage is enhanced, but the device structure and manufacturing process become more complex
Solution Approach 1:
The patent merges the bias pad structure with the buried oxide layer formation process. The conductive interlayers within the stacked oxide structure serve dual functions as both electrical biasing elements and integral parts of the insulating layer, eliminating the need for separate bias pad structures and reducing overall device complexity.
Solution Approach 2:
The conductive interlayers in the stacked oxide structure perform multiple functions: they provide electrical biasing to control the electrical environment, serve as part of the insulating barrier structure, and enable leakage current reduction. This multi-functionality reduces the need for additional dedicated structures.
3Adaptability or versatility
If multiple oxide layers with conductive interlayers are used to achieve high breakdown voltage, then the operating voltage window is extended, but the manufacturing process steps and process complexity increase
Solution Approach 1:
The patent incorporates conductive interlayers during the oxide layer formation process itself, rather than adding them as separate post-processing steps. This preliminary integration allows the stacked structure to be built up layer-by-layer using standard deposition and doping processes already present in the manufacturing flow.
Solution Approach 2:
The patent achieves high breakdown voltage by changing the structural parameters of the oxide layer from a single thick layer to multiple thinner layers with conductive interlayers. This parameter change allows the use of standard thin oxide deposition parameters while achieving the cumulative breakdown voltage effect through the stacked configuration.
Data Source
AI summary
A method of making a semiconductor device includes manufacturing a bias layer over a buried oxide layer. The method further includes growing a layer of semiconductor material over the bias layer. The method further includes forming a transistor in the layer of semiconductor material, wherein the bias layer is between the transistor and a substrate. The method further includes forming a first deep trench isolation structure (DTI) extending through the layer of semiconductor material and contacting the substrate. The method further includes forming a first bias contact extending through the layer of the semiconductor material and electrically connecting to the bias layer. The method further includes forming a contact extending through the DTI to contact the substrate, wherein the contact is separated from the bias layer.