Buried Bit Line Semiconductor Device Bulb-Type Trenches
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Solution Overview
Problem
Conventional semiconductor devices with buried bit lines face challenges such as pattern leaning due to high aspect ratio etching processes and increased parasitic capacitance between adjacent bit lines, which affect data retention and integration density.
Innovation Solution
The semiconductor device employs bulb-type trenches and supporters to form active regions, bisecting them into body lines and burying bit lines within these regions, using insulation materials to prevent punch-through and reduce parasitic capacitance by spacing bit lines apart and eliminating the need for high aspect ratio etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high aspect ratio etching process is used to form deep preliminary body line to prevent punch-through, then punch-through prevention is improved, but pattern leaning occurs and manufacturing precision deteriorates
Solution Approach 1:
An insulation layer is formed at the bottom of the trench before the bit line is formed. This preliminary action provides immediate punch-through prevention without requiring excessive trench depth, thereby avoiding the high aspect ratio etching that causes pattern leaning. The insulation layer is deposited conformally and then planarized, creating a stable base before subsequent processing steps.
Solution Approach 2:
The aspect ratio of the trench is optimized by changing the etching parameters and trench depth. Instead of etching to the full required depth in one step (which creates high aspect ratio), the process uses a two-stage approach: first forming a shallower trench with controlled aspect ratio, then adding the insulation layer to achieve the same electrical isolation effect with reduced geometric aspect ratio, preventing pattern leaning.
2Object-affected harmful factors
If interval between adjacent buried bit lines is increased to reduce parasitic capacitance, then parasitic capacitance is reduced, but area occupied by bit lines increases
Solution Approach 1:
Instead of increasing the physical spacing between bit lines, the patent uses an insulation layer that copies the electrical isolation function of large spacing. The insulation material creates an electrical barrier that replicates the effect of increased separation distance, reducing parasitic capacitance without requiring additional lateral or vertical space.
Solution Approach 2:
An insulation layer with specific dielectric properties is introduced between adjacent bit lines. This composite structure combines the conductive bit line material with the insulating material, creating a system where the insulation layer's low dielectric constant reduces parasitic capacitance while maintaining compact bit line spacing for high integration density.
3Productivity
If channel length of MOSFET is reduced to increase integration density, then integration density is improved, but data retention characteristics deteriorate
Solution Approach 1:
The patent transitions from planar channel transistors to vertical channel transistors, changing the channel direction from lateral to vertical. This dimensional change allows the channel length to be extended in the vertical direction while maintaining a compact lateral footprint, thereby improving data retention without sacrificing integration density. The vertical channel is formed by etching deep trenches and filling them with semiconductor material.
Solution Approach 2:
The insulation layer is formed at the bottom of the trench before the vertical channel and bit line are created. This preliminary action establishes proper electrical isolation and channel structure from the beginning, ensuring that even with reduced lateral dimensions for high density, the vertical channel length can be sufficiently long to maintain data retention characteristics.
Data Source
AI summary
A method for fabricating a semiconductor device includes etching semiconductor substrate to form bulb-type trenches that define a plurality of active regions in the semiconductor substrate; forming a supporter in each of the bulb-type trenches; dividing each active region, of the plurality of active regions, into a pair of body lines by forming a trench through each active region; and forming a bit line in each body line of the pair of body lines.