Buried Bit Line Parasitic Capacitance Reduction
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Solution Overview
Problem
The existing semiconductor device fabrication technologies face challenges in reducing parasitic capacitance between adjacent buried bit lines, which can lead to device malfunction as the integration level increases and the distance between bit lines narrows, due to difficulties in forming uniform and reproducible OSC structures.
Innovation Solution
The method involves forming buried bit lines in the bodies rather than in the trenches between them, using a BSC process that includes etching a substrate to create trenches, forming silicidation preventing regions, and performing a full silicidation process to create metal silicide buried bit lines that are co-planar with the trench bottoms, thereby reducing parasitic capacitance and ensuring uniform open part formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between adjacent buried bit lines is reduced to increase integration, then the degree of integration is improved, but parasitic capacitance between bit lines increases
Solution Approach 1:
A trench filling layer is introduced as an intermediary material between adjacent buried bit lines. This layer acts as a dielectric mediator that reduces the parasitic capacitance coupling between the bit lines, enabling closer spacing while maintaining signal integrity and reducing unwanted capacitive effects.
Solution Approach 2:
The trench filling layer is selectively placed only in the regions between adjacent buried bit lines, where parasitic capacitance is the primary concern. This localized approach targets the specific problem area without affecting other parts of the device structure, optimizing the balance between integration density and capacitance reduction.
2Object-generated harmful factors
If OSC process is used to connect buried bit lines with bodies, then direct contact is achieved reducing parasitic capacitance, but uniform and reproducible structure formation becomes difficult
Solution Approach 1:
Instead of forming open parts in the protective layer to expose sidewalls for bit line contact (OSC process), the invention inverts the approach by forming the buried bit lines directly in the substrate and filling the trenches between them. This eliminates the need for complex OSC processing while achieving comparable or superior electrical contact and reducing uniformity issues.
Solution Approach 2:
The invention extracts and eliminates the problematic OSC process steps (forming protective layer, creating open parts, exposing sidewalls) that cause manufacturing variability. By directly forming bit lines in the substrate and filling trenches, the complex multi-step OSC process is replaced with a simpler, more reproducible fabrication sequence.
3Device complexity
If buried bit lines are formed in trenches between bodies, then connection structure is simplified, but parasitic capacitance between adjacent bit lines increases
Solution Approach 1:
The trench filling layer serves as a dielectric intermediary between adjacent buried bit lines, reducing parasitic capacitance coupling. This mediator material is specifically placed in the spaces between bit lines to provide electrical isolation while maintaining the simplified connection structure advantage.
Solution Approach 2:
The structure combines the conductive buried bit lines with the dielectric trench filling layer to create a composite configuration. This composite structure leverages the electrical conductivity of the bit lines for signal transmission while utilizing the insulating properties of the filling layer to reduce parasitic capacitance between adjacent lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance between adjacent buried bit lines, improves signal transfer characteristics, and prevents short-circuiting and punch-through phenomena, enhancing the reliability and performance of semiconductor devices.
Implementation Method 1
performing a silicidation process on the sidewalls of the plurality of bodies to form buried bit lines in each body
Data Source
AI summary
A semiconductor device including buried bit lines formed of a metal silicide and silicidation preventing regions formed in a substrate under trenches that separate the buried bit lines.