Buried Bit Line Composite Structure for Memory Device Resistance
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Solution Overview
Problem
Miniaturization of memory cells in semiconductor devices leads to increased bit line capacitance, resulting in higher contact resistance, which can cause short channel effects and junction leakage, and traditional bit line structures fail to effectively address these issues due to narrow dimensions and step height coupling problems.
Innovation Solution
The introduction of buried bit lines with a barrier layer and conducting layer, replacing the traditional polysilicon layer, to reduce contact resistance and improve current conductance, while allowing for thinner word lines to prevent short channel effects, comprising a substrate with buried word lines, digital contacts, a patterned insulating layer, a liner layer, and a cap layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are miniaturized to increase density, then the number of memory cells increases, but bit line capacitance increases causing higher contact resistance
Solution Approach 1:
The patent changes the material parameters of the bit line from traditional polysilicon to a composite structure of barrier layer (e.g., titanium nitride) and conducting layer (e.g., tungsten or copper). This material parameter change reduces contact resistance while allowing continued miniaturization of memory cells, thus resolving the contradiction between increasing cell density and maintaining low contact resistance.
Solution Approach 2:
The patent employs a composite bit line structure consisting of a barrier layer and a conducting layer. The barrier layer prevents diffusion and provides adhesion, while the conducting layer provides low resistance. This composite material approach enables the bit line to withstand higher current densities and maintain low contact resistance even as memory cells are miniaturized and more cells are connected to each bit line.
2Reliability
If junction depth is increased to reduce contact resistance, then contact resistance decreases, but short channel effect and junction leakage increase
Solution Approach 1:
The patent changes the material composition parameter of the bit line from polysilicon to barrier layer + conducting layer composite. This material parameter change allows the bit line to achieve low contact resistance without increasing junction depth, thereby avoiding the harmful effects of short channel effect and junction leakage while maintaining reliable electrical contact.
3Ease of manufacture
If traditional polysilicon bit lines are used, then manufacturing is simpler, but contact resistance is high and current conductance is insufficient
Solution Approach 1:
The patent replaces traditional single-material polysilicon bit lines with a composite structure of barrier layer and conducting layer. This composite material approach improves contact resistance and current conductance performance while maintaining compatibility with existing semiconductor manufacturing processes, thus resolving the contradiction between manufacturing simplicity and electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration decreases contact resistance, enhances current conductance, and increases the stability of the memory device by preventing short channel effects, allowing for higher performance and efficient integration of subsequent elements.
Implementation Method 1
The barrier layer is arranged on the patterned insulating layer and the liner layer, and covers the contact holes in a uniform conformal manner
Implementation Method 2
The conducting layer is arranged on the barrier layer and filled in the contact holes
Data Source
AI summary
A memory device comprises a substrate, a plurality of buried word lines, a plurality of digital contacts, a patterned insulating layer, a liner layer, a plurality of buried bit lines, and a cap layer. The buried word lines are arranged in the substrate in parallel along a first direction. Each of the digital contacts is arranged between one pair of the neighboring buried word lines. The patterned insulating layer is arranged on the buried word lines, having a plurality of contact holes opposite to the digital contacts. The liner layer is arranged on the substrate, and abuts the patterned insulating layer. The buried bit lines are arranged in parallel along a second direction different from the first direction. The cap layer arranged to cover the buried bit lines.