Buried Bit Line Contact Formation Using Polysilicon Diffusion
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Solution Overview
Problem
In semiconductor manufacturing, the scaling down of DRAMs below 40 nm grade is challenging due to issues with leakage current and increased resistance when using titanium nitride or tungsten layers, and the etch back process for bit line formation often results in substrate loss and bit line removal.
Innovation Solution
A method involving the formation of silicon line patterns, insulating layers, a conductive pattern, and an amorphous carbon spacer to prevent substrate loss during bit line contact formation, using plasma etching and polysilicon doping to create a junction region without stripping metal spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If titanium nitride layer or tungsten layer is used to form the junction, then the contact is formed, but leakage current increases
Solution Approach 1:
The patent uses a metal layer (titanium nitride or tungsten) that is intentionally designed to be removed after serving its temporary purpose of enabling diffusion. This disposable layer facilitates the formation of the junction during the diffusion process and is then stripped away, preventing the harmful effect of TiSi2 generation while maintaining contact functionality.
Solution Approach 2:
The metal layer is formed in advance before the diffusion process to prepare the contact structure. This preliminary action ensures that the contact region is properly prepared for dopant diffusion, and the metal layer serves as a temporary facilitator that is removed afterward to prevent leakage current issues.
2Object-generated harmful factors
If polysilicon layer is used to prevent leakage current, then leakage current is reduced, but resistance increases
Solution Approach 1:
The patent employs a metal layer as a temporary, disposable structure that enables the formation of low-resistance contacts through diffusion without the resistance penalty of polysilicon. The metal layer is removed after serving its function, avoiding the creation of high-resistance polysilicon contacts while still achieving the goal of preventing leakage current.
3Ease of manufacture
If etch back process is performed after contact is formed by diffusing metal layer, then bit line is formed, but semiconductor substrate is lost
Solution Approach 1:
The bit line contact open region is formed in advance through selective removal of the interlayer insulating layer before the diffusion process. This preliminary action defines the exact region where the contact will be formed, preventing any loss of semiconductor substrate during subsequent etch back processes while ensuring proper contact formation.
Solution Approach 2:
The patent applies different treatments to different regions: the interlayer insulating layer is selectively removed only in the specific region where the bit line contact needs to be formed, while the rest of the structure remains intact. This localized approach prevents substrate loss while enabling contact formation.
4Ease of manufacture
If contact is formed after bit line is formed, then bit line contact is created, but bit line is removed when stripping metal spacer
Solution Approach 1:
The patent extracts or removes the interlayer insulating layer selectively to expose only the specific region where the bit line contact needs to be formed. This extraction approach allows contact formation without requiring metal spacer stripping that would remove the bit line, thus preventing bit line loss while maintaining the desired contact structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains the channel region size as transistors shrink, reduces leakage current, and prevents substrate and bit line loss during etch back processes, enhancing integration density and reducing parasitic capacitance.
Implementation Method 1
using plasma etching and polysilicon doping to create a junction region
Implementation Method 2
diffusing the dopants from the polysilicon pattern into the second silicon line pattern through the bit line contact open region to form a junction region
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming silicon line patterns in a semiconductor substrate, forming an insulating layer over the silicon line patterns, forming a conductive pattern between the silicon line patterns, forming a spacer over the substrate, forming an interlayer insulating layer between the silicon line patterns, removing the spacer on one side of the silicon line patterns to expose the conductive pattern, forming a bit line contact open region by removing the interlayer insulating layer, forming a polysilicon pattern to cover the bit line contact open region, and forming a junction region diffused to the silicon line pattern through the bit line contact open region. Thereby, a stacked structure of a titanium layer and a polysilicon layer are stably formed when forming a buried bit line and a bit line contact is formed using diffusion of the polysilicon layer to prevent leakage current.