Buried Bit Line Fabrication via Metal Deposition

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Solution Overview

Problem

The existing methods for fabricating semiconductor devices with buried bit lines face challenges in reducing the resistance of these bit lines, which is essential for improving signal transmission performance, due to physical limitations and complex fabrication processes, especially in achieving low-resistant metal-based buried bit lines.

Innovation Solution

The semiconductor device incorporates a punch stop region, pillar structures with a stack of sacrificial and active layers, and buried bit lines formed by selectively etching a conductive layer between the pillar structures, along with isolation layers to separate and reduce capacitance between adjacent bit lines, allowing for the use of metal layers to improve signal transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If ion-implantation doping method is used to form buried bit lines, then the fabrication process is simple, but the resistance of buried bit lines is large due to physical limitation in doping concentration

Engineering Contradiction:

Improvefabrication process simplicityVSAvoidburied bit line resistance

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent changes the material parameter from doped semiconductor to metal, fundamentally altering the resistance characteristic. By forming buried bit lines using metal layers (such as tungsten or copper) instead of relying on ion-implantation doping, the resistance is dramatically reduced while maintaining fabrication simplicity through standard metal deposition and etching processes.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If metal is used for buried bit lines to reduce resistance, then the resistance decreases, but the fabrication process becomes complicated and difficult

Engineering Contradiction:

Improveburied bit line resistanceVSAvoidfabrication process complexity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies preliminary action by forming the metal layer for buried bit lines before forming the pillar structures. The metal layer is deposited across the entire substrate, then pillar structures are formed on top of it. Subsequent selective removal of metal and sacrificial layers creates the buried bit line structure. This sequence simplifies the process by avoiding complex post-pillar metal formation steps.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent uses a sacrificial layer as an intermediary element. The sacrificial layer is formed between the metal layer and the active layer, serving as a placeholder that defines the future buried bit line position. After pillar structures are formed, the sacrificial layer is selectively removed to expose and isolate the metal buried bit lines, simplifying the overall fabrication sequence.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Area of stationary object

If buried bit lines are formed closer to active pillars to reduce cell area, then the cell area decreases, but the capacitance between adjacent bit lines increases

Engineering Contradiction:

Improveunit cell areaVSAvoidcapacitance between adjacent bit lines

Core Design Contradiction:

Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

The patent uses isolation layers as intermediary elements between adjacent buried bit lines. These isolation layers (such as oxide or nitride) are formed between closely spaced metal bit lines, providing electrical isolation that reduces parasitic capacitance. This allows the bit lines to be positioned closer together for smaller cell area while maintaining low capacitance through the dielectric barrier.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in semiconductor devices with low-resistant buried bit lines that enhance signal transmission performance and simplifies the fabrication process, increasing manufacturing productivity while reducing capacitance between adjacent bit lines.

Implementation Method 1

forming a plurality of buried bit lines under the pillar structures by selectively etching the conductive layer

Methodology Applied

Scientific EffectSelective etching:

Data Source

PatentUS9236327B2Semiconductor device with buried bit line and method for fabricating the same

Publication Date: 2016.01.12 SK HYNIX INC

AI summary

A semiconductor device includes: a punch stop region formed in a substrate; a plurality of buried bit lines formed over the substrate; a plurality of pillar structures formed over the buried bit lines; a plurality of word lines extending to intersect the buried bit lines and being in contact with the pillar structures; and an isolation layer isolating the word lines from the buried bit lines.