Buried Bit Line Pillar Stability via Two-Stage Etching
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Solution Overview
Problem
High aspect ratios in trench structures lead to pillars bending or collapsing during the fabrication of buried bit lines, particularly in the 40 nm process, resulting in lower yields and increased fabrication costs.
Innovation Solution
A method involving the creation of wider masked regions compared to first etched regions, with two-stage trench formation to support pillars, using negative photoresist materials and specific layer deposition techniques to prevent pillar collapse and enhance structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the aspect ratio of the trench is increased to reduce cell size, then the area occupied by the transistor is reduced, but the pillar is more likely to bend or fracture
Solution Approach 1:
The patent divides the single trench formation process into two sequential etching stages. First, a shallow first trench is etched with a first etching condition, then a deeper second trench is etched with a second etching condition. This segmentation allows the pillar to maintain structural integrity during fabrication while achieving the required high aspect ratio for reduced cell size, preventing pillar bending or fracture.
Solution Approach 2:
The patent performs preliminary actions by forming the first trench and filling it with packing material before forming the second trench. This preliminary structuring provides mechanical support to the pillar during subsequent processing steps, enabling the pillar to withstand the stresses of high aspect ratio formation without bending or collapsing.
2Productivity
If the aspect ratio of the trench is increased to accommodate more transistors in unit area, then the transistor density is improved, but the yield decreases due to pillar bending or collapse
Solution Approach 1:
The patent segments the trench formation into two distinct etching processes with different conditions. The first etching creates a shallow trench that is then filled with packing material, providing mechanical reinforcement. The second etching completes the deep trench formation. This segmentation enables high transistor density through high aspect ratio trenches while maintaining fabrication yield by preventing pillar collapse during processing.
Solution Approach 2:
The patent changes etching parameters between the two stages: using a first etching condition for the initial shallow trench, then a second etching condition for the deeper trench formation. This parameter change allows precise control over trench depth and pillar stability at each stage, achieving high transistor density without sacrificing manufacturing precision or yield.
3Device complexity
If conventional single-stage etching is used to form trenches, then the fabrication process is simple, but the pillar structure cannot support high aspect ratios without bending or collapsing
Solution Approach 1:
The patent divides the trench formation into two sequential etching stages with different conditions, transforming a simple single-stage process into a multi-stage process. This increased process complexity is necessary to achieve the structural strength required for high aspect ratio pillars, allowing the pillar to support itself during fabrication without bending or collapsing.
Solution Approach 2:
The patent performs preliminary trench formation and packing material filling before completing the deep trench etching. This preliminary action creates a structurally reinforced configuration that enables the pillar to maintain strength during subsequent processing, justifying the increased fabrication process complexity to achieve reliable high aspect ratio structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents pillar bending and collapse, reduces fabrication costs, and allows for smaller cell sizes, improving yield and reducing defective fractions in sub-40 nm processes.
Implementation Method 1
a plurality of photoresist layers are deposited on the surface of the substrate to form the masked regions
Implementation Method 2
implanting first conductive ions into two sidewalls of each first trench to form two bit lines respectively on two sidewalls of each first pillar
Implementation Method 3
depositing a blocking layer on the surfaces of the etching retard layer and the packing material through an ALD (Atomic Layer Deposition) or MLD (Molecular Layer Deposition) technique
Data Source
AI summary
A method for fabricating buried bit lines comprises steps of: defining a plurality of parallel masked regions and a plurality of first etched regions each forming between any two neighboring masked regions on a surface of a substrate, and wherein the masked region is wider than the first etched region; etching the first etched regions to form a plurality of first trenches and a plurality of first pillars; forming two bit lines respectively on two sidewalls of each first trench; etching the first pillars to form a plurality of second pillars corresponding to the bit lines. The present invention uses a two-stage etching process to prevent pillars from bending or collapsing due to high aspect ratio. Moreover, the present invention has a simple process and is able to reduce cost and decrease cell size.