Buried Bit Line Structure Without Contact for Lower Resistance

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Solution Overview

Problem

Existing buried bit lines in semiconductor memory devices, such as DRAM, suffer from high resistance and a complicated fabrication process due to the bit line contact structure.

Innovation Solution

A method involving forming a first trench in a substrate, covering it with a protective layer, etching to create second trenches, forming a passivation layer, and etching the side walls to create grooves for dielectric layers, which are then filled to form buried bit lines, eliminating the need for a bit line contact structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If existing buried bit lines with bit line contact structure are used, then the bit line can be connected to the transistor, but the resistance is high and the fabrication process is complicated

Engineering Contradiction:
Improveelectrical connectionVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the bit line contact structure from the semiconductor device. By removing this intermediate contact layer, the bit line is directly connected to the transistor drain region, simplifying the fabrication process while maintaining electrical connectivity. This extraction principle directly addresses the contradiction by removing the source of complexity without compromising the electrical connection function.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If existing buried bit lines with bit line contact structure are used, then the bit line can be connected to the transistor, but the resistance is high

Engineering Contradiction:
Improveelectrical connectionVSAvoidresistance
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent extracts and eliminates the bit line contact structure that was causing high resistance. By removing this intermediate layer and establishing direct contact between the bit line and transistor drain, the electrical resistance is reduced, improving energy efficiency while maintaining reliable electrical connection.

Inventive Principle:
Principle #2Taking out (Extraction)

3Ease of operation

If bit line contact structure is used to connect bit line to transistor, then electrical connection is achieved, but the fabrication process becomes complicated

Engineering Contradiction:
Improveelectrical connectionVSAvoidfabrication process
Core Design Contradiction:
Ease of operationVSEase of manufacture

Solution Approach 1:

The patent removes the bit line contact structure from the device architecture. This extraction eliminates the need for additional fabrication steps associated with forming and patterning the contact structure, thereby simplifying the manufacturing process while preserving the essential electrical connection between bit line and transistor.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the bit line formation process with the transistor fabrication process. By integrating these two previously separate processes into one unified flow, the fabrication becomes simpler and more efficient, eliminating the need for distinct bit line contact structure formation steps.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12432908B2Semiconductor structure and method for fabricating same
Publication Date: 2025.09.30 CHANGXIN MEMORY TECH INC
  • US12432908B2 patent drawing
  • US12432908B2 patent drawing
  • US12432908B2 patent drawing

AI summary

Embodiments relate to a semiconductor structure and a method for fabricating the same. The method includes: providing a substrate, a first trench being formed in the substrate; forming a protective layer in the first trench, the protective layer covering a side wall and a bottom of the first trench; etching the protective layer and the substrate at the bottom of the first trench to form second trenches; forming a passivation layer at a bottom of each of the second trenches; and etching a side wall of each of the second trenches to form a groove, and forming a dielectric layer in the groove. The method can eliminate a process of forming a bit line contact structure, thereby reducing resistance of a bit line and simplifying fabrication processes of the bit line.