Buried Bit Line Semiconductor Device Fabrication
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Solution Overview
Problem
Conventional semiconductor devices with buried bit lines face challenges in reducing resistance and complexity, particularly in achieving low resistance buried bit lines and simplifying fabrication processes for mass production, due to limitations in doping concentration and structural difficulties.
Innovation Solution
The semiconductor device incorporates trenches with partially filled buried bit lines, a source/drain layer, and stack patterns with a channel layer, where the buried bit lines are formed using a metallic layer and the stack patterns are bonded to the substrate, allowing for low resistance and reduced capacitance between adjacent bit lines, simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If impurity ions are implanted into the substrate to form an impurity region for the buried bit line, then the buried bit line can be formed, but the resistance of the buried bit line increases due to limitations in doping concentration
Solution Approach 1:
The patent changes the material parameter of the buried bit line from doped semiconductor (with resistance limitations) to metallic material (with inherently low resistance). This parameter change allows the buried bit line to achieve low resistance without being constrained by doping concentration limits, directly resolving the contradiction between forming the buried bit line and maintaining low resistance.
2Object-affected harmful factors
If a metallic layer is used to form the buried bit line to reduce resistance, then the resistance decreases, but the fabrication procedure becomes complicated and requires high difficulty fabricating technologies
Solution Approach 1:
The patent segments the fabrication process into distinct stages: first forming the metallic buried bit line in trenches, then subsequently forming the semiconductor structures. This segmentation allows the metallic layer to be deposited using standard techniques without requiring complex one-sided contact structures, simplifying the overall fabrication procedure while maintaining low resistance.
Solution Approach 2:
The metallic buried bit line is formed preliminarily before the semiconductor structures are created. By preparing the low-resistance metallic pathway in advance, the patent avoids the need for complex subsequent steps to create electrical connections, thereby simplifying the fabrication process while ensuring low resistance from the outset.
3Area of stationary object
If the area of the semiconductor device is reduced to increase degree of integration, then the plane area decreases, but the channel length may be adversely influenced
Solution Approach 1:
The patent transitions from a planar channel structure to a vertical channel structure by standing the channel up perpendicular to the substrate. This dimensional change allows the channel length to extend in the vertical direction rather than the horizontal plane, enabling reduced plane area while maintaining adequate channel length for device operation.
Data Source
AI summary
A semiconductor device includes trenches defined in a substrate, buried bit lines partially filling the trenches, a first source/drain layer filling remaining portions of the trenches on the buried bit lines, stack patterns having a channel layer and a second source/drain layer stacked therein and bonded to the first source/drain layer, wherein the channel layer contacts with the first source/drain layer, and word lines crossing with the buried bit lines and disposed adjacent to sidewalls of the channel layer.