Buried Bit Line Silicidation for Parasitic Capacitance Reduction
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Solution Overview
Problem
Existing semiconductor devices with buried bit lines face challenges in reducing parasitic capacitance between adjacent bit lines, which affects device performance as the distance between bit lines narrows, leading to increased capacitance and potential operational issues.
Innovation Solution
A method involving the formation of buried bit lines through a double-side-contact process and full silicidation, where a silicon-containing buffer layer is used to fill open parts between silicon bodies, and a metal-containing layer is formed to create metal silicide bit lines, reducing parasitic capacitance by ensuring sufficient separation between adjacent bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between adjacent buried bit lines is narrowed to increase integration, then device density is improved, but parasitic capacitance between bit lines increases
Solution Approach 1:
The patent transitions from a planar bit line arrangement to a three-dimensional structure where bit lines are buried within trenches at different vertical levels. This dimensional change allows bit lines to be positioned closer horizontally while maintaining electrical isolation through vertical separation and dielectric layers, thereby increasing device density without proportionally increasing parasitic capacitance.
Solution Approach 2:
The patent introduces dielectric layers and isolation structures as intermediary elements between adjacent buried bit lines. These intermediary layers physically separate the bit lines and provide electrical insulation, reducing the direct capacitive coupling that would occur if bit lines were placed close together without isolation. This allows narrow spacing while controlling parasitic capacitance.
2Device complexity
If conventional OSC process is used to connect buried bit line with vertical channel transistor, then manufacturing complexity is reduced, but uniformity and reproducibility of OSC structure deteriorates
Solution Approach 1:
The patent performs preliminary actions by pre-forming the buried bit lines in trenches and pre-defining the contact regions on the vertical channel transistors before the actual connection process. This preliminary structuring ensures that when the connection is made, both elements are already positioned and sized correctly, leading to uniform and reproducible OSC structures without requiring complex real-time adjustment processes.
Solution Approach 2:
The patent employs parameter changes by systematically controlling the dimensions, depths, and spacing of trenches and bit lines through standardized fabrication parameters. By establishing consistent parameters for trench depth, bit line width, and separation distances, the process achieves uniformity and reproducibility across different manufacturing batches while maintaining manageable complexity.
3Object-generated harmful factors
If buried bit line is brought into direct contact with vertical channel transistor without contact plug, then parasitic capacitance is reduced, but connection reliability may deteriorate
Solution Approach 1:
The patent employs composite material structures at the bit line-transistor interface, combining the conductive bit line material with intermediate silicide layers and dielectric materials. This composite structure provides both low parasitic capacitance through direct contact and high connection reliability through the multi-layer construction that ensures good electrical bonding and mechanical stability.
Solution Approach 2:
The patent applies local quality by creating different material compositions and structural characteristics at specific locations: the bit line itself has one material property, the immediate interface region has different properties optimized for electrical contact, and the surrounding isolation regions have properties optimized for electrical insulation. This localized optimization simultaneously reduces parasitic capacitance and ensures connection reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces parasitic capacitance between adjacent buried bit lines, improves device performance by minimizing resistance and maintaining structural stability, and prevents issues like bit line cutting and leaning.
Implementation Method 1
forming a buried bit line in the body by siliciding the buffer layer and a portion of the body between the buffer layer
Data Source
AI summary
A method for fabricating a semiconductor device includes forming at least one body having two sidewalls by vertically etching a semiconductor substrate, forming a protective layer having open parts that expose portions of the both sidewalls of the body, forming a buffer layer that fills the open parts, and forming a buried bit line in the body by siliciding the buffer layer and a portion of the body between the buffer layer.