Buried Bit Line Vertical Transistor Fabrication
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Solution Overview
Problem
The reduction in physical dimensions of transistors leads to severe short channel effects and decreased ON current, while conventional solutions like enhanced dopant concentration increase leakage current, and existing vertical transistor structures aim to enhance operating speed and integration but require improved structural design and channel control.
Innovation Solution
A method for forming a buried bit line structure with a circle-segment-shaped buried bit line and a vertical transistor, including a substrate with a trench, widened bottom surface, doping areas, and a conductive layer, allowing for self-aligned fabrication and streamlined process to enhance operating speed and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If physical dimensions of transistors are reduced to accelerate operating speed and miniaturize electronic devices, then operating speed and integration are improved, but severe short channel effects occur and ON current decreases
Solution Approach 1:
The patent transitions from a planar transistor structure to a vertical transistor structure by forming the channel region vertically beneath the gate electrode. This dimensional change allows the channel to extend deeper into the substrate, providing better gate control over the channel and reducing short channel effects while maintaining smaller footprint dimensions for higher integration.
Solution Approach 2:
The vertical transistor structure nests the channel region within the substrate beneath the gate, creating a stacked configuration where the gate electrode overlays the channel region. This nested arrangement enables the gate to control the channel from above, improving electrostatic control and mitigating short channel effects in scaled devices.
2Power
If dopant concentration in the channel region is enhanced to maintain ON current, then ON current is improved, but leakage current increases and device reliability decreases
Solution Approach 1:
The patent implements local quality by creating a highly doped buried bit line region adjacent to the channel while keeping the channel region itself with optimized doping. The buried bit line is selectively doped with phosphorus or arsenic to provide high conductivity for bit line connections without requiring the channel to have high dopant concentration, thus maintaining low leakage current.
3Reliability
If vertical transistor structure is used to alleviate short channel effect, then short channel effect is improved, but structural design and channel control require aggressive improvements
Solution Approach 1:
The patent segments the transistor structure into distinct functional regions: a buried bit line region with high doping for conductivity, a channel region with optimized doping for current control, and a gate electrode for control. This segmentation allows each region to be independently optimized and formed through separate processing steps, simplifying the overall structural design while achieving excellent short channel effect control.
4Ease of manufacture
If conventional fabrication methods are used for buried bit line and vertical transistor, then manufacturing process is simple, but operating speed and integration are not enhanced
Solution Approach 1:
The patent merges the formation of the buried bit line and the vertical transistor channel region into a single etching process. The etch process simultaneously defines both the line-shaped trench for the buried bit line and the channel region, allowing these structures to be formed concurrently rather than through separate sequential steps. This reduces overall process complexity while enabling advanced integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables accurate formation of buried bit lines and vertical transistors, improving operating speed and integration by reducing short channel effects and leakage current, while allowing for simultaneous fabrication of buried bit lines and shallow trench isolation.
Implementation Method 1
a doping area is formed in the substrate adjacent to the curved bottom surface
Data Source
AI summary
A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line.