Buried Bit Line DRAM Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
As the density of transistors in DRAM increases, issues such as parasitic capacitance between bit lines and between bit lines and storage node contacts become more severe, leading to RC delay and potential failure of induction amplifiers, while sub-threshold leakage current problems worsen, affecting device performance and reliability.
Innovation Solution
The method involves forming a semiconductor device with trench isolation structures, buried bit line structures, and word line structures. The buried bit line structures are formed within the semiconductor substrate, while the word line structures and active regions are formed on the surface above the functional regions, thereby reducing leakage current and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor density is increased, then memory capacity is improved, but parasitic capacitance between bit lines and storage node contacts increases
Solution Approach 1:
The patent transitions from planar bit line configuration to three-dimensional stacked configuration. Bit lines are arranged in multiple layers (first bit line in source region, second bit line in drain region) vertically stacked above the channel, reducing parasitic capacitance by separating bit lines in the vertical dimension while maintaining high transistor density.
Solution Approach 2:
The bit line function is segmented into multiple independent bit lines at different vertical levels. The first bit line is positioned in the source region while the second bit line is positioned in the drain region, allowing independent control and reducing mutual interference and parasitic capacitance between bit lines and storage node contacts.
2Quantity of substance
If transistor size is reduced, then device density is improved, but sub-threshold leakage current increases
Solution Approach 1:
The patent applies different doping characteristics to source and drain regions. The source region has first doping characteristics while the drain region has second doping characteristics, creating local quality variations that optimize carrier injection and extraction while reducing sub-threshold leakage current in scaled devices.
Solution Approach 2:
The patent employs composite material structures including semiconductor-superlattice-semiconductor configurations in the channel region, and combines different doping characteristics in source and drain regions. These composite structures provide better electrostatic control and reduce leakage current in miniaturized devices.
3Quantity of substance
If bit line and storage node contact spacing is reduced, then device density is improved, but RC delay increases
Solution Approach 1:
The patent moves bit lines from planar arrangement to vertical stacking in three dimensions. The first bit line is positioned in the source region and the second bit line in the drain region, with word lines extending in the first direction. This vertical arrangement reduces the horizontal spacing requirements and minimizes RC delay while achieving higher device density.
Data Source
AI summary
The present disclosure provides a semiconductor device and a manufacturing method thereof. The method for manufacturing a semiconductor device includes: providing a semiconductor substrate, with a plurality of trench isolation structures and a plurality of functional regions between the trench isolation structures being formed; forming a buried bit line structure, the buried bit line structure being formed in the semiconductor substrate; and forming a word line structure and a plurality of active regions, the word line structures and the active regions being formed on a surface of the semiconductor substrate and located above the functional regions.