Buried Bitline Vertical DRAM Structure for Floating Body Suppression
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Solution Overview
Problem
Current dynamic random-access memory (DRAM) devices face challenges such as the floating body effect and high common bitline resistance due to the scaling of semiconductor fin structures, particularly in 4F2 vertical DRAM designs, which result in off-leakage current and high resistance issues.
Innovation Solution
The implementation of a buried bitline formed using a low-temperature ion implant with a heavy N+ dopant and a contact formed using a low-temperature ion implant with a heavy N++ dopant, along with a bottom silicon-germanium source/drain, which reduces back injection efficiency and contact resistance, and avoids uncontrolled thermal diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 4F2 vertical DRAM devices are scaled to smaller dimensions, then device density and integration are improved, but floating body effect and off-leakage current increase
Solution Approach 1:
The patent extracts the bitline from the traditional fin structure and forms it as a separate buried bitline structure within the substrate. This separation removes the floating body effect source by providing a dedicated doping region for the bitline, eliminating the harmful charge accumulation that causes off-leakage current while maintaining high device density.
Solution Approach 2:
The patent applies local quality by creating heavily doped N+ regions specifically at the bitline location within the substrate, while maintaining different doping characteristics in other regions. This localized heavy doping ensures proper bitline formation and eliminates floating body effects in the critical bitline region without affecting other device characteristics.
2Ease of manufacture
If conventional doping methods are used, then manufacturing process is simple, but thermal diffusion causes uncontrolled dopant distribution
Solution Approach 1:
The patent changes the temperature parameter during ion implantation to below 0°C. This parameter change reduces thermal diffusion of dopants during the implantation process, enabling precise control of dopant distribution and concentration profiles without requiring complex masking or multiple implantation steps.
Solution Approach 2:
The patent performs preliminary actions by forming the buried bitline structure before forming the vertical fin structures. This sequence allows the bitline doping to be established first with precise control, preventing subsequent thermal processes from affecting bitline dopant distribution, while still using standard ion implantation equipment.
3Loss of time
If standard doping temperatures are used, then processing is faster, but dopant diffusion is uncontrolled
Solution Approach 1:
The patent changes the substrate temperature parameter to below 0°C during ion implantation. This temperature reduction suppresses thermal diffusion mechanisms that would otherwise cause uncontrolled dopant spread, achieving precise dopant concentration control while maintaining relatively fast processing speeds by avoiding lengthy thermal annealing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a floating body-free device with lower contact resistance and improved performance by reducing parasitic bipolar junction transistor back injection efficiency and avoiding thermal diffusion issues, thus addressing the deficiencies of prior art.
Implementation Method 1
forming a buried bitline in the base by directing ions into the base while the substrate is at a temperature below 0° C.
Implementation Method 2
forming a buried bitline formed using a low-temperature ion implant with a heavy N+ dopant
Data Source
AI summary
Disclosed herein are approaches for forming a dynamic random-access memory device (DRAM). An example DRAM device may include a plurality of pillars extending from a base of a substrate, a gate formed around the plurality of pillars, and a buried bitline formed within the base, wherein an upper surface of the buried bitline is recessed below an upper surface of the base. The DRAM device may further include a bottom source/drain formed beneath the plurality of pillars, and a contact formed in the bottom source/drain, between the plurality of pillars.